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561 lines
17 KiB
561 lines
17 KiB
/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/msm/msm-bus-ids.h>
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&soc {
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/* QUPv3 North Instances
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* North 0 : SE 0
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* North 1 : SE 1
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* North 2 : SE 2
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* North 3 : SE 3
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* North 4 : SE 4
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* North 5 : SE 5
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*/
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qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
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compatible = "qcom,qupv3-geni-se";
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reg = <0x8c0000 0x2000>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-bus-ids =
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<MSM_BUS_MASTER_QUP_CORE_0 MSM_BUS_SLAVE_QUP_CORE_0>,
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<MSM_BUS_MASTER_QUP_0 MSM_BUS_SLAVE_EBI_CH0>;
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qcom,iommu-atomic-ctx;
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iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb {
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compatible = "qcom,qupv3-geni-se-cb";
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iommus = <&apps_smmu 0x43 0x0>;
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};
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};
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/* GPI */
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gpi_dma0: qcom,gpi-dma@800000 {
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#dma-cells = <5>;
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compatible = "qcom,gpi-dma";
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reg = <0x800000 0x60000>;
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reg-names = "gpi-top";
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interrupts = <0 244 0>, <0 245 0>, <0 246 0>, <0 247 0>,
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<0 248 0>, <0 249 0>, <0 250 0>, <0 251 0>,
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<0 252 0>, <0 253 0>;
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qcom,max-num-gpii = <10>;
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qcom,gpii-mask = <0x1f>;
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qcom,ev-factor = <2>;
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iommus = <&apps_smmu 0x56 0x0>;
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qcom,smmu-cfg = <0x1>;
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qcom,gpi-ee-offset = <0x10000>;
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qcom,iova-range = <0x0 0x100000 0x0 0x100000>;
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status = "ok";
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};
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/* SPI */
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qupv3_se0_spi: spi@880000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x880000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_spi_active>;
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pinctrl-1 = <&qupv3_se0_spi_sleep>;
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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dmas = <&gpi_dma0 0 0 1 64 0>,
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<&gpi_dma0 1 0 1 64 0>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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qupv3_se1_spi: spi@884000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x884000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se1_spi_active>;
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pinctrl-1 = <&qupv3_se1_spi_sleep>;
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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dmas = <&gpi_dma0 0 1 1 64 0>,
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<&gpi_dma0 1 1 1 64 0>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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qupv3_se3_spi: spi@88c000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x88c000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se3_spi_active>;
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pinctrl-1 = <&qupv3_se3_spi_sleep>;
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interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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dmas = <&gpi_dma0 0 3 1 64 0>,
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<&gpi_dma0 1 3 1 64 0>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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qupv3_se5_spi: spi@894000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x894000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se5_spi_active>;
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pinctrl-1 = <&qupv3_se5_spi_sleep>;
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interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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dmas = <&gpi_dma0 0 5 1 64 0>,
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<&gpi_dma0 1 5 1 64 0>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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/* I2C */
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qupv3_se0_i2c: i2c@880000 {
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compatible = "qcom,i2c-geni";
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reg = <0x880000 0x4000>;
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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dmas = <&gpi_dma0 0 0 3 64 0>,
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<&gpi_dma0 1 0 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_i2c_active>;
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pinctrl-1 = <&qupv3_se0_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se1_i2c: i2c@884000 {
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compatible = "qcom,i2c-geni";
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reg = <0x884000 0x4000>;
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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dmas = <&gpi_dma0 0 1 3 64 0>,
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<&gpi_dma0 1 1 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se1_i2c_active>;
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pinctrl-1 = <&qupv3_se1_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se2_i2c: i2c@888000 {
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compatible = "qcom,i2c-geni";
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reg = <0x888000 0x4000>;
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interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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dmas = <&gpi_dma0 0 2 3 64 0>,
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<&gpi_dma0 1 2 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se2_i2c_active>;
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pinctrl-1 = <&qupv3_se2_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se3_i2c: i2c@88c000 {
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compatible = "qcom,i2c-geni";
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reg = <0x88c000 0x4000>;
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interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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dmas = <&gpi_dma0 0 3 3 64 0>,
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<&gpi_dma0 1 3 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se3_i2c_active>;
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pinctrl-1 = <&qupv3_se3_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se4_i2c: i2c@890000 {
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compatible = "qcom,i2c-geni";
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reg = <0x890000 0x4000>;
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interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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dmas = <&gpi_dma0 0 4 3 64 0>,
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<&gpi_dma0 1 4 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se4_i2c_active>;
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pinctrl-1 = <&qupv3_se4_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se5_i2c: i2c@894000 {
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compatible = "qcom,i2c-geni";
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reg = <0x894000 0x4000>;
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interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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dmas = <&gpi_dma0 0 5 3 64 0>,
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<&gpi_dma0 1 5 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se5_i2c_active>;
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pinctrl-1 = <&qupv3_se5_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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/* HSUART: BT used instance */
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qupv3_se3_4uart: qcom,qup_uart@88c000 {
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compatible = "qcom,msm-geni-serial-hs";
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reg = <0x88c000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "active", "sleep";
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pinctrl-0 = <&qupv3_se3_default_ctsrtsrx>,
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<&qupv3_se3_default_tx>;
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pinctrl-1 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>,
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<&qupv3_se3_tx>;
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pinctrl-2 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>,
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<&qupv3_se3_tx>;
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interrupts-extended = <&intc GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
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<&tlmm 41 IRQ_TYPE_LEVEL_HIGH>;
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qcom,wrapper-core = <&qupv3_0>;
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qcom,wakeup-byte = <0xFD>;
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status = "disabled";
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};
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/* QUPv3 South Instances
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* South 0 : SE 6
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* South 1 : SE 7
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* South 2 : SE 8
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* South 3 : SE 9
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* South 4 : SE 10
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* South 5 : SE 11
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*/
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qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
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compatible = "qcom,qupv3-geni-se";
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reg = <0xac0000 0x2000>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-bus-ids =
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<MSM_BUS_MASTER_QUP_CORE_1 MSM_BUS_SLAVE_QUP_CORE_1>,
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<MSM_BUS_MASTER_QUP_1 MSM_BUS_SLAVE_EBI_CH0>;
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qcom,iommu-atomic-ctx;
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iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb {
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compatible = "qcom,qupv3-geni-se-cb";
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iommus = <&apps_smmu 0x4c3 0x0>;
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};
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};
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/* GPI */
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gpi_dma1: qcom,gpi-dma@a00000 {
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#dma-cells = <5>;
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compatible = "qcom,gpi-dma";
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reg = <0xa00000 0x60000>;
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reg-names = "gpi-top";
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interrupts = <0 645 0>, <0 646 0>, <0 647 0>, <0 648 0>,
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<0 649 0>, <0 650 0>, <0 651 0>, <0 652 0>,
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<0 653 0>, <0 654 0>;
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qcom,max-num-gpii = <10>;
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qcom,gpii-mask = <0x3f>;
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qcom,ev-factor = <2>;
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iommus = <&apps_smmu 0x4d6 0x0>;
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qcom,smmu-cfg = <0x1>;
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qcom,gpi-ee-offset = <0x10000>;
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qcom,iova-range = <0x0 0x100000 0x0 0x100000>;
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status = "ok";
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};
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/* SPI */
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qupv3_se6_spi: spi@a80000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xa80000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se6_spi_active>;
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pinctrl-1 = <&qupv3_se6_spi_sleep>;
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interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_1>;
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dmas = <&gpi_dma1 0 0 1 64 0>,
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<&gpi_dma1 1 0 1 64 0>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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qupv3_se8_spi: spi@a88000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xa88000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se8_spi_active>;
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pinctrl-1 = <&qupv3_se8_spi_sleep>;
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interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_1>;
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dmas = <&gpi_dma1 0 2 1 64 0>,
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<&gpi_dma1 1 2 1 64 0>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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qupv3_se10_spi: spi@a90000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xa90000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se10_spi_active>;
|
|
pinctrl-1 = <&qupv3_se10_spi_sleep>;
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
spi-max-frequency = <50000000>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
dmas = <&gpi_dma1 0 4 1 64 0>,
|
|
<&gpi_dma1 1 4 1 64 0>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se11_spi: spi@a94000 {
|
|
compatible = "qcom,spi-geni";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xa94000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>,
|
|
<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se11_spi_active>;
|
|
pinctrl-1 = <&qupv3_se11_spi_sleep>;
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
|
spi-max-frequency = <50000000>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
dmas = <&gpi_dma1 0 5 1 64 0>,
|
|
<&gpi_dma1 1 5 1 64 0>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
/* I2C */
|
|
qupv3_se6_i2c: i2c@a80000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa80000 0x4000>;
|
|
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>,
|
|
<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
dmas = <&gpi_dma1 0 0 3 64 0>,
|
|
<&gpi_dma1 1 0 3 64 0>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se6_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se6_i2c_sleep>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se7_i2c: i2c@a84000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa84000 0x4000>;
|
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>,
|
|
<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
dmas = <&gpi_dma1 0 1 3 64 0>,
|
|
<&gpi_dma1 1 1 3 64 0>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se7_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se7_i2c_sleep>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se8_i2c: i2c@a88000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa88000 0x4000>;
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>,
|
|
<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
dmas = <&gpi_dma1 0 2 3 64 0>,
|
|
<&gpi_dma1 1 2 3 64 0>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se8_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se8_i2c_sleep>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se9_i2c: i2c@a8c000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa8c000 0x4000>;
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>,
|
|
<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
dmas = <&gpi_dma1 0 3 3 64 0>,
|
|
<&gpi_dma1 1 3 3 64 0>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se9_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se9_i2c_sleep>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se10_i2c: i2c@a90000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa90000 0x4000>;
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>,
|
|
<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
dmas = <&gpi_dma1 0 4 3 64 0>,
|
|
<&gpi_dma1 1 4 3 64 0>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se10_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se10_i2c_sleep>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se11_i2c: i2c@a94000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa94000 0x4000>;
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>,
|
|
<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
dmas = <&gpi_dma1 0 5 3 64 0>,
|
|
<&gpi_dma1 1 5 3 64 0>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se11_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se11_i2c_sleep>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se8_2uart: qcom,qup_uart@a88000 {
|
|
compatible = "qcom,msm-geni-console";
|
|
reg = <0xa88000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>,
|
|
<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se8_2uart_active>;
|
|
pinctrl-1 = <&qupv3_se8_2uart_sleep>;
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
};
|
|
|