/* Copyright (c) 2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include &soc { /* QUPv3 North Instances * North 0 : SE 0 * North 1 : SE 1 * North 2 : SE 2 * North 3 : SE 3 * North 4 : SE 4 * North 5 : SE 5 */ qupv3_0: qcom,qupv3_0_geni_se@8c0000 { compatible = "qcom,qupv3-geni-se"; reg = <0x8c0000 0x2000>; qcom,msm-bus,num-paths = <2>; qcom,msm-bus,vectors-bus-ids = , ; qcom,iommu-atomic-ctx; iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb { compatible = "qcom,qupv3-geni-se-cb"; iommus = <&apps_smmu 0x43 0x0>; }; }; /* GPI */ gpi_dma0: qcom,gpi-dma@800000 { #dma-cells = <5>; compatible = "qcom,gpi-dma"; reg = <0x800000 0x60000>; reg-names = "gpi-top"; interrupts = <0 244 0>, <0 245 0>, <0 246 0>, <0 247 0>, <0 248 0>, <0 249 0>, <0 250 0>, <0 251 0>, <0 252 0>, <0 253 0>; qcom,max-num-gpii = <10>; qcom,gpii-mask = <0x1f>; qcom,ev-factor = <2>; iommus = <&apps_smmu 0x56 0x0>; qcom,smmu-cfg = <0x1>; qcom,gpi-ee-offset = <0x10000>; qcom,iova-range = <0x0 0x100000 0x0 0x100000>; status = "ok"; }; /* SPI */ qupv3_se0_spi: spi@880000 { compatible = "qcom,spi-geni"; #address-cells = <1>; #size-cells = <0>; reg = <0x880000 0x4000>; reg-names = "se_phys"; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se0_spi_active>; pinctrl-1 = <&qupv3_se0_spi_sleep>; interrupts = ; spi-max-frequency = <50000000>; qcom,wrapper-core = <&qupv3_0>; dmas = <&gpi_dma0 0 0 1 64 0>, <&gpi_dma0 1 0 1 64 0>; dma-names = "tx", "rx"; status = "disabled"; }; qupv3_se1_spi: spi@884000 { compatible = "qcom,spi-geni"; #address-cells = <1>; #size-cells = <0>; reg = <0x884000 0x4000>; reg-names = "se_phys"; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>, <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se1_spi_active>; pinctrl-1 = <&qupv3_se1_spi_sleep>; interrupts = ; spi-max-frequency = <50000000>; qcom,wrapper-core = <&qupv3_0>; dmas = <&gpi_dma0 0 1 1 64 0>, <&gpi_dma0 1 1 1 64 0>; dma-names = "tx", "rx"; status = "disabled"; }; qupv3_se3_spi: spi@88c000 { compatible = "qcom,spi-geni"; #address-cells = <1>; #size-cells = <0>; reg = <0x88c000 0x4000>; reg-names = "se_phys"; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se3_spi_active>; pinctrl-1 = <&qupv3_se3_spi_sleep>; interrupts = ; spi-max-frequency = <50000000>; qcom,wrapper-core = <&qupv3_0>; dmas = <&gpi_dma0 0 3 1 64 0>, <&gpi_dma0 1 3 1 64 0>; dma-names = "tx", "rx"; status = "disabled"; }; qupv3_se5_spi: spi@894000 { compatible = "qcom,spi-geni"; #address-cells = <1>; #size-cells = <0>; reg = <0x894000 0x4000>; reg-names = "se_phys"; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>, <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se5_spi_active>; pinctrl-1 = <&qupv3_se5_spi_sleep>; interrupts = ; spi-max-frequency = <50000000>; qcom,wrapper-core = <&qupv3_0>; dmas = <&gpi_dma0 0 5 1 64 0>, <&gpi_dma0 1 5 1 64 0>; dma-names = "tx", "rx"; status = "disabled"; }; /* I2C */ qupv3_se0_i2c: i2c@880000 { compatible = "qcom,i2c-geni"; reg = <0x880000 0x4000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; dmas = <&gpi_dma0 0 0 3 64 0>, <&gpi_dma0 1 0 3 64 0>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se0_i2c_active>; pinctrl-1 = <&qupv3_se0_i2c_sleep>; qcom,wrapper-core = <&qupv3_0>; status = "disabled"; }; qupv3_se1_i2c: i2c@884000 { compatible = "qcom,i2c-geni"; reg = <0x884000 0x4000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>, <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; dmas = <&gpi_dma0 0 1 3 64 0>, <&gpi_dma0 1 1 3 64 0>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se1_i2c_active>; pinctrl-1 = <&qupv3_se1_i2c_sleep>; qcom,wrapper-core = <&qupv3_0>; status = "disabled"; }; qupv3_se2_i2c: i2c@888000 { compatible = "qcom,i2c-geni"; reg = <0x888000 0x4000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>, <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; dmas = <&gpi_dma0 0 2 3 64 0>, <&gpi_dma0 1 2 3 64 0>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se2_i2c_active>; pinctrl-1 = <&qupv3_se2_i2c_sleep>; qcom,wrapper-core = <&qupv3_0>; status = "disabled"; }; qupv3_se3_i2c: i2c@88c000 { compatible = "qcom,i2c-geni"; reg = <0x88c000 0x4000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; dmas = <&gpi_dma0 0 3 3 64 0>, <&gpi_dma0 1 3 3 64 0>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se3_i2c_active>; pinctrl-1 = <&qupv3_se3_i2c_sleep>; qcom,wrapper-core = <&qupv3_0>; status = "disabled"; }; qupv3_se4_i2c: i2c@890000 { compatible = "qcom,i2c-geni"; reg = <0x890000 0x4000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>, <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; dmas = <&gpi_dma0 0 4 3 64 0>, <&gpi_dma0 1 4 3 64 0>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se4_i2c_active>; pinctrl-1 = <&qupv3_se4_i2c_sleep>; qcom,wrapper-core = <&qupv3_0>; status = "disabled"; }; qupv3_se5_i2c: i2c@894000 { compatible = "qcom,i2c-geni"; reg = <0x894000 0x4000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>, <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; dmas = <&gpi_dma0 0 5 3 64 0>, <&gpi_dma0 1 5 3 64 0>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se5_i2c_active>; pinctrl-1 = <&qupv3_se5_i2c_sleep>; qcom,wrapper-core = <&qupv3_0>; status = "disabled"; }; /* HSUART: BT used instance */ qupv3_se3_4uart: qcom,qup_uart@88c000 { compatible = "qcom,msm-geni-serial-hs"; reg = <0x88c000 0x4000>; reg-names = "se_phys"; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; pinctrl-names = "default", "active", "sleep"; pinctrl-0 = <&qupv3_se3_default_ctsrtsrx>, <&qupv3_se3_default_tx>; pinctrl-1 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>, <&qupv3_se3_tx>; pinctrl-2 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>, <&qupv3_se3_tx>; interrupts-extended = <&intc GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, <&tlmm 41 IRQ_TYPE_LEVEL_HIGH>; qcom,wrapper-core = <&qupv3_0>; qcom,wakeup-byte = <0xFD>; status = "disabled"; }; /* QUPv3 South Instances * South 0 : SE 6 * South 1 : SE 7 * South 2 : SE 8 * South 3 : SE 9 * South 4 : SE 10 * South 5 : SE 11 */ qupv3_1: qcom,qupv3_1_geni_se@ac0000 { compatible = "qcom,qupv3-geni-se"; reg = <0xac0000 0x2000>; qcom,msm-bus,num-paths = <2>; qcom,msm-bus,vectors-bus-ids = , ; qcom,iommu-atomic-ctx; iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb { compatible = "qcom,qupv3-geni-se-cb"; iommus = <&apps_smmu 0x4c3 0x0>; }; }; /* GPI */ gpi_dma1: qcom,gpi-dma@a00000 { #dma-cells = <5>; compatible = "qcom,gpi-dma"; reg = <0xa00000 0x60000>; reg-names = "gpi-top"; interrupts = <0 645 0>, <0 646 0>, <0 647 0>, <0 648 0>, <0 649 0>, <0 650 0>, <0 651 0>, <0 652 0>, <0 653 0>, <0 654 0>; qcom,max-num-gpii = <10>; qcom,gpii-mask = <0x3f>; qcom,ev-factor = <2>; iommus = <&apps_smmu 0x4d6 0x0>; qcom,smmu-cfg = <0x1>; qcom,gpi-ee-offset = <0x10000>; qcom,iova-range = <0x0 0x100000 0x0 0x100000>; status = "ok"; }; /* SPI */ qupv3_se6_spi: spi@a80000 { compatible = "qcom,spi-geni"; #address-cells = <1>; #size-cells = <0>; reg = <0xa80000 0x4000>; reg-names = "se_phys"; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>, <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se6_spi_active>; pinctrl-1 = <&qupv3_se6_spi_sleep>; interrupts = ; spi-max-frequency = <50000000>; qcom,wrapper-core = <&qupv3_1>; dmas = <&gpi_dma1 0 0 1 64 0>, <&gpi_dma1 1 0 1 64 0>; dma-names = "tx", "rx"; status = "disabled"; }; qupv3_se8_spi: spi@a88000 { compatible = "qcom,spi-geni"; #address-cells = <1>; #size-cells = <0>; reg = <0xa88000 0x4000>; reg-names = "se_phys"; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se8_spi_active>; pinctrl-1 = <&qupv3_se8_spi_sleep>; interrupts = ; spi-max-frequency = <50000000>; qcom,wrapper-core = <&qupv3_1>; dmas = <&gpi_dma1 0 2 1 64 0>, <&gpi_dma1 1 2 1 64 0>; dma-names = "tx", "rx"; status = "disabled"; }; qupv3_se10_spi: spi@a90000 { compatible = "qcom,spi-geni"; #address-cells = <1>; #size-cells = <0>; reg = <0xa90000 0x4000>; reg-names = "se_phys"; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se10_spi_active>; pinctrl-1 = <&qupv3_se10_spi_sleep>; interrupts = ; spi-max-frequency = <50000000>; qcom,wrapper-core = <&qupv3_1>; dmas = <&gpi_dma1 0 4 1 64 0>, <&gpi_dma1 1 4 1 64 0>; dma-names = "tx", "rx"; status = "disabled"; }; qupv3_se11_spi: spi@a94000 { compatible = "qcom,spi-geni"; #address-cells = <1>; #size-cells = <0>; reg = <0xa94000 0x4000>; reg-names = "se_phys"; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>, <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se11_spi_active>; pinctrl-1 = <&qupv3_se11_spi_sleep>; interrupts = ; spi-max-frequency = <50000000>; qcom,wrapper-core = <&qupv3_1>; dmas = <&gpi_dma1 0 5 1 64 0>, <&gpi_dma1 1 5 1 64 0>; dma-names = "tx", "rx"; status = "disabled"; }; /* I2C */ qupv3_se6_i2c: i2c@a80000 { compatible = "qcom,i2c-geni"; reg = <0xa80000 0x4000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>, <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; dmas = <&gpi_dma1 0 0 3 64 0>, <&gpi_dma1 1 0 3 64 0>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se6_i2c_active>; pinctrl-1 = <&qupv3_se6_i2c_sleep>; qcom,wrapper-core = <&qupv3_1>; status = "disabled"; }; qupv3_se7_i2c: i2c@a84000 { compatible = "qcom,i2c-geni"; reg = <0xa84000 0x4000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>, <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; dmas = <&gpi_dma1 0 1 3 64 0>, <&gpi_dma1 1 1 3 64 0>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se7_i2c_active>; pinctrl-1 = <&qupv3_se7_i2c_sleep>; qcom,wrapper-core = <&qupv3_1>; status = "disabled"; }; qupv3_se8_i2c: i2c@a88000 { compatible = "qcom,i2c-geni"; reg = <0xa88000 0x4000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; dmas = <&gpi_dma1 0 2 3 64 0>, <&gpi_dma1 1 2 3 64 0>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se8_i2c_active>; pinctrl-1 = <&qupv3_se8_i2c_sleep>; qcom,wrapper-core = <&qupv3_1>; status = "disabled"; }; qupv3_se9_i2c: i2c@a8c000 { compatible = "qcom,i2c-geni"; reg = <0xa8c000 0x4000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>, <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; dmas = <&gpi_dma1 0 3 3 64 0>, <&gpi_dma1 1 3 3 64 0>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se9_i2c_active>; pinctrl-1 = <&qupv3_se9_i2c_sleep>; qcom,wrapper-core = <&qupv3_1>; status = "disabled"; }; qupv3_se10_i2c: i2c@a90000 { compatible = "qcom,i2c-geni"; reg = <0xa90000 0x4000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; dmas = <&gpi_dma1 0 4 3 64 0>, <&gpi_dma1 1 4 3 64 0>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se10_i2c_active>; pinctrl-1 = <&qupv3_se10_i2c_sleep>; qcom,wrapper-core = <&qupv3_1>; status = "disabled"; }; qupv3_se11_i2c: i2c@a94000 { compatible = "qcom,i2c-geni"; reg = <0xa94000 0x4000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>, <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; dmas = <&gpi_dma1 0 5 3 64 0>, <&gpi_dma1 1 5 3 64 0>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se11_i2c_active>; pinctrl-1 = <&qupv3_se11_i2c_sleep>; qcom,wrapper-core = <&qupv3_1>; status = "disabled"; }; qupv3_se8_2uart: qcom,qup_uart@a88000 { compatible = "qcom,msm-geni-console"; reg = <0xa88000 0x4000>; reg-names = "se_phys"; clock-names = "se-clk", "m-ahb", "s-ahb"; clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se8_2uart_active>; pinctrl-1 = <&qupv3_se8_2uart_sleep>; interrupts = ; qcom,wrapper-core = <&qupv3_1>; status = "disabled"; }; };