Commit Graph

60 Commits (55b70a0300b873c0ec7ea6e33752af56f41250ce)

Author SHA1 Message Date
Ralf Baechle 64bfca5cd8 [MIPS] Cache: Provide more information on cache policy on bootup. 18 years ago
Ralf Baechle 21a151d8ca [MIPS] checkfiles: Fix "need space after that ','" errors. 18 years ago
Ralf Baechle 10cc352907 [MIPS] Allow hardwiring of the CPU type to a single type for optimization. 18 years ago
Ralf Baechle db813fe5a7 [MIPS] Avoid indexed cacheops. 18 years ago
Ralf Baechle 641e97f318 [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code. 18 years ago
Ralf Baechle e001e52801 [MIPS] Replace use of stext with _stext. 18 years ago
Fuxin Zhang 2a21c7300b [MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2 18 years ago
Ralf Baechle 617667ba72 [MIPS] Avoid dupliate D-cache flush on R400C / R4400 SC and MC variants. 18 years ago
Atsushi Nemoto 0550d9d13e [MIPS] Remove redundant r4k_blast_icache() calls 18 years ago
Atsushi Nemoto c59a0f15be [MIPS] Remove __flush_icache_page 19 years ago
Ralf Baechle a00f631018 [MIPS] c-r4k: Convert init functions from inline to __init. 19 years ago
Atsushi Nemoto f6502791d7 [MIPS] Do not use drop_mmu_context to flusing other task's VIPT I-cache. 19 years ago
Ralf Baechle 585fa72493 [MIPS] Retire flush_icache_page from mm use. 19 years ago
Ralf Baechle df586d59a4 [MIPS] c-r4k: Typo fix. 19 years ago
Yoichi Yuasa 2874fe5533 [MIPS] vr41xx: Replace magic number for P4K bit with symbol. 19 years ago
Yoichi Yuasa 1058ecda9b [MIPS] vr41xx: Changed workaround to recommended method 19 years ago
Yoichi Yuasa 4e8ab36182 [MIPS] VR41xx: Set VR41_CONF_BP only for PrId 0x0c80. 19 years ago
Ralf Baechle fc5d2d279f [MIPS] Use the proper technical term for naming some of the cache macros. 19 years ago
Jörn Engel 6ab3d5624e Remove obsolete #include <linux/config.h> 19 years ago
Ralf Baechle 2e78ae3f48 [MIPS] 74K: Assume it will also have an AR bit in config7 19 years ago
Ralf Baechle beab375a48 [MIPS] Treat CPUs with AR bit as physically indexed. 19 years ago
Chris Dearman 73f403527b [MIPS] Fix handling of 0 length I & D caches. 19 years ago
Chris Dearman 9318c51acd [MIPS] MIPS32/MIPS64 secondary cache management 19 years ago
Sergei Shtylyov 9370b35175 [MIPS] Save write-only Config.OD from being clobbered 19 years ago
Kumba 44d921b246 [MIPS] Treat R14000 like R10000. 19 years ago
Ralf Baechle 7f3f1d01a9 [MIPS] Fix deadlock on MP with cache aliases. 19 years ago
Nigel Stephens 98a41de99a [MIPS] Add missing 34K processor IDs 19 years ago
Atsushi Nemoto 3c68da798a [MIPS] Use __ffs() instead of ffs() for waybit calculation. 19 years ago
Ralf Baechle 7e3bfc7cfc [MIPS] Handle IDE PIO cache aliases on SMP. 19 years ago
Atsushi Nemoto 67a3f6de93 [MIPS] Fix tx49_blast_icache32_page_indexed. 19 years ago
Atsushi Nemoto de862b488e [MIPS] TX49XX has prefetch. 19 years ago
Atsushi Nemoto de62893bc0 [MIPS] local_r4k_flush_cache_page fix 19 years ago
Ralf Baechle 4debe4f963 [MIPS] Initialize S-cache function pointers even on S-cache-less CPUs. 19 years ago
Atsushi Nemoto 41700e7399 [MIPS] Add protected_blast_icache_range, blast_icache_range, etc. 19 years ago
Atsushi Nemoto d4264f1839 [MIPS] Remove wrong __user tags. 19 years ago
Ralf Baechle e7958bb90d MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1. 19 years ago
Ralf Baechle 6ec25809c1 Rename page argument of flush_cache_page to something more descriptive. 20 years ago
Ralf Baechle 02cf211968 Cleanup the mess in cpu_cache_init. 20 years ago
Thiemo Seufer 10a3dabddd Add/Fix missing bit of R4600 hit cacheop workaround. 20 years ago
Thiemo Seufer 02fe2c9ce3 Minor code cleanup. 20 years ago
Thiemo Seufer d8748a3abf More .set push/pop. 20 years ago
Thiemo Seufer 330cfe016b Let r4600 PRID detection match only legacy CPUs, cleanups. 20 years ago
Ralf Baechle 1d40cfcd34 Avoid SMP cacheflushes. This is a minor optimization of startup but 20 years ago
Ralf Baechle e01402b115 More AP / SP bits for the 34K, the Malta bits and things. Still wants 20 years ago
Ralf Baechle ec74e361f1 Mark a few variables __read_mostly. 20 years ago
Ralf Baechle cc61c1fede MIPS R2 instruction hazard handling. 20 years ago
Thiemo Seufer ba5187dbb4 Better interface to run uncached cache setup code. 20 years ago
Ralf Baechle fe00f943e0 Sparseify MIPS. 20 years ago
Pete Popov e3ad1c23ba Base Au1200 2.6 support. 20 years ago
Thiemo Seufer 26a51b270f Use intermediate variable. 20 years ago