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[MIPS] Allow hardwiring of the CPU type to a single type for optimization.

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This saves a few k on systems which only ever ship with a single CPU type.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
tirimbino
Ralf Baechle 18 years ago
parent aeffdbbaff
commit 10cc352907
20 changed files with 89 additions and 86 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 2
      arch/mips/dec/ecc-berr.c
  2. 2
      arch/mips/dec/kn02xa-berr.c
  3. 8
      arch/mips/dec/prom/init.c
  4. 6
      arch/mips/kernel/traps.c
  5. 12
      arch/mips/mm/c-r4k.c
  6. 6
      arch/mips/mm/c-tx39.c
  7. 4
      arch/mips/mm/dma-default.c
  8. 2
      arch/mips/mm/pg-r4k.c
  9. 10
      arch/mips/mm/tlbex.c
  10. 2
      arch/mips/oprofile/common.c
  11. 4
      arch/mips/oprofile/op_model_mipsxx.c
  12. 2
      arch/mips/pci/pci-vr41xx.c
  13. 8
      arch/mips/vr41xx/common/bcu.c
  14. 16
      arch/mips/vr41xx/common/cmu.c
  15. 2
      arch/mips/vr41xx/common/giu.c
  16. 76
      arch/mips/vr41xx/common/icu.c
  17. 4
      arch/mips/vr41xx/common/pmu.c
  18. 2
      arch/mips/vr41xx/common/rtc.c
  19. 2
      arch/mips/vr41xx/common/siu.c
  20. 5
      include/asm-mips/cpu-features.h

2
arch/mips/dec/ecc-berr.c
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@ -263,7 +263,7 @@ static inline void dec_kn03_be_init(void)
*/
*mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) |
KN03_MCR_CORRECT;
if (current_cpu_data.cputype == CPU_R4400SC)
if (current_cpu_type() == CPU_R4400SC)
*mbcs |= KN4K_MB_CSR_EE;
fast_iob();
}

2
arch/mips/dec/kn02xa-berr.c
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@ -132,7 +132,7 @@ void __init dec_kn02xa_be_init(void)
volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
/* For KN04 we need to make sure EE (?) is enabled in the MB. */
if (current_cpu_data.cputype == CPU_R4000SC)
if (current_cpu_type() == CPU_R4000SC)
*mbcs |= KN4K_MB_CSR_EE;
fast_iob();

8
arch/mips/dec/prom/init.c
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@ -108,8 +108,8 @@ void __init prom_init(void)
/* Were we compiled with the right CPU option? */
#if defined(CONFIG_CPU_R3000)
if ((current_cpu_data.cputype == CPU_R4000SC) ||
(current_cpu_data.cputype == CPU_R4400SC)) {
if ((current_cpu_type() == CPU_R4000SC) ||
(current_cpu_type() == CPU_R4400SC)) {
static char r4k_msg[] __initdata =
"Please recompile with \"CONFIG_CPU_R4x00 = y\".\n";
printk(cpu_msg);
@ -119,8 +119,8 @@ void __init prom_init(void)
#endif
#if defined(CONFIG_CPU_R4X00)
if ((current_cpu_data.cputype == CPU_R3000) ||
(current_cpu_data.cputype == CPU_R3000A)) {
if ((current_cpu_type() == CPU_R3000) ||
(current_cpu_type() == CPU_R3000A)) {
static char r3k_msg[] __initdata =
"Please recompile with \"CONFIG_CPU_R3000 = y\".\n";
printk(cpu_msg);

6
arch/mips/kernel/traps.c
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@ -954,7 +954,7 @@ asmlinkage void do_reserved(struct pt_regs *regs)
*/
static inline void parity_protection_init(void)
{
switch (current_cpu_data.cputype) {
switch (current_cpu_type()) {
case CPU_24K:
case CPU_34K:
case CPU_5KC:
@ -1549,8 +1549,8 @@ void __init trap_init(void)
set_except_vector(12, handle_ov);
set_except_vector(13, handle_tr);
if (current_cpu_data.cputype == CPU_R6000 ||
current_cpu_data.cputype == CPU_R6000A) {
if (current_cpu_type() == CPU_R6000 ||
current_cpu_type() == CPU_R6000A) {
/*
* The R6000 is the only R-series CPU that features a machine
* check exception (similar to the R4000 cache error) and

12
arch/mips/mm/c-r4k.c
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@ -328,7 +328,7 @@ static inline void local_r4k___flush_cache_all(void * args)
r4k_blast_dcache();
r4k_blast_icache();
switch (current_cpu_data.cputype) {
switch (current_cpu_type()) {
case CPU_R4000SC:
case CPU_R4000MC:
case CPU_R4400SC:
@ -377,10 +377,10 @@ static inline void local_r4k_flush_cache_mm(void * args)
* R4000SC and R4400SC indexed S-cache ops also invalidate primary
* caches, so we can bail out early.
*/
if (current_cpu_data.cputype == CPU_R4000SC ||
current_cpu_data.cputype == CPU_R4000MC ||
current_cpu_data.cputype == CPU_R4400SC ||
current_cpu_data.cputype == CPU_R4400MC) {
if (current_cpu_type() == CPU_R4000SC ||
current_cpu_type() == CPU_R4000MC ||
current_cpu_type() == CPU_R4400SC ||
current_cpu_type() == CPU_R4400MC) {
r4k_blast_scache();
return;
}
@ -1197,7 +1197,7 @@ static void __init coherency_setup(void)
* this bit and; some wire it to zero, others like Toshiba had the
* silly idea of putting something else there ...
*/
switch (current_cpu_data.cputype) {
switch (current_cpu_type()) {
case CPU_R4000PC:
case CPU_R4000SC:
case CPU_R4000MC:

6
arch/mips/mm/c-tx39.c
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@ -69,7 +69,7 @@ static void tx39h_dma_cache_wback_inv(unsigned long addr, unsigned long size)
/* TX39H2,TX39H3 */
static inline void tx39_blast_dcache_page(unsigned long addr)
{
if (current_cpu_data.cputype != CPU_TX3912)
if (current_cpu_type() != CPU_TX3912)
blast_dcache16_page(addr);
}
@ -307,7 +307,7 @@ static __init void tx39_probe_cache(void)
TX39_CONF_DCS_SHIFT));
current_cpu_data.icache.linesz = 16;
switch (current_cpu_data.cputype) {
switch (current_cpu_type()) {
case CPU_TX3912:
current_cpu_data.icache.ways = 1;
current_cpu_data.dcache.ways = 1;
@ -341,7 +341,7 @@ void __init tx39_cache_init(void)
tx39_probe_cache();
switch (current_cpu_data.cputype) {
switch (current_cpu_type()) {
case CPU_TX3912:
/* TX39/H core (writethru direct-map cache) */
flush_cache_all = tx39h_flush_icache_all;

4
arch/mips/mm/dma-default.c
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@ -35,8 +35,8 @@ static inline unsigned long dma_addr_to_virt(dma_addr_t dma_addr)
static inline int cpu_is_noncoherent_r10000(struct device *dev)
{
return !plat_device_is_coherent(dev) &&
(current_cpu_data.cputype == CPU_R10000 ||
current_cpu_data.cputype == CPU_R12000);
(current_cpu_type() == CPU_R10000 ||
current_cpu_type() == CPU_R12000);
}
void *dma_alloc_noncoherent(struct device *dev, size_t size,

2
arch/mips/mm/pg-r4k.c
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@ -354,7 +354,7 @@ void __init build_clear_page(void)
store_offset = 0;
if (cpu_has_prefetch) {
switch (current_cpu_data.cputype) {
switch (current_cpu_type()) {
case CPU_TX49XX:
/* TX49 supports only Pref_Load */
pref_offset_clear = 0;

10
arch/mips/mm/tlbex.c
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@ -827,7 +827,7 @@ static __initdata u32 final_handler[64];
*/
static __init void __maybe_unused build_tlb_probe_entry(u32 **p)
{
switch (current_cpu_data.cputype) {
switch (current_cpu_type()) {
/* Found by experiment: R4600 v2.0 needs this, too. */
case CPU_R4600:
case CPU_R5000:
@ -860,7 +860,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
case tlb_indexed: tlbw = i_tlbwi; break;
}
switch (current_cpu_data.cputype) {
switch (current_cpu_type()) {
case CPU_R4000PC:
case CPU_R4000SC:
case CPU_R4000MC:
@ -1158,7 +1158,7 @@ static __init void build_adjust_context(u32 **p, unsigned int ctx)
unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
switch (current_cpu_data.cputype) {
switch (current_cpu_type()) {
case CPU_VR41XX:
case CPU_VR4111:
case CPU_VR4121:
@ -1188,7 +1188,7 @@ static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
* in a different cacheline or a load instruction, probably any
* memory reference, is between them.
*/
switch (current_cpu_data.cputype) {
switch (current_cpu_type()) {
case CPU_NEVADA:
i_LW(p, ptr, 0, ptr);
GET_CONTEXT(p, tmp); /* get context reg */
@ -1872,7 +1872,7 @@ void __init build_tlb_refill_handler(void)
*/
static int run_once = 0;
switch (current_cpu_data.cputype) {
switch (current_cpu_type()) {
case CPU_R2000:
case CPU_R3000:
case CPU_R3000A:

2
arch/mips/oprofile/common.c
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@ -74,7 +74,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
struct op_mips_model *lmodel = NULL;
int res;
switch (current_cpu_data.cputype) {
switch (current_cpu_type()) {
case CPU_5KC:
case CPU_20KC:
case CPU_24K:

4
arch/mips/oprofile/op_model_mipsxx.c
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@ -222,7 +222,7 @@ static inline int n_counters(void)
{
int counters;
switch (current_cpu_data.cputype) {
switch (current_cpu_type()) {
case CPU_R10000:
counters = 2;
break;
@ -274,7 +274,7 @@ static int __init mipsxx_init(void)
#endif
op_model_mipsxx_ops.num_counters = counters;
switch (current_cpu_data.cputype) {
switch (current_cpu_type()) {
case CPU_20KC:
op_model_mipsxx_ops.cpu_type = "mips/20K";
break;

2
arch/mips/pci/pci-vr41xx.c
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@ -228,7 +228,7 @@ static int __init vr41xx_pciu_init(void)
else
pciu_write(PCIEXACCREG, 0);
if (current_cpu_data.cputype == CPU_VR4122)
if (current_cpu_type() == CPU_VR4122)
pciu_write(PCITRDYVREG, TRDYV(setup->wait_time_limit_from_irdy_to_trdy));
pciu_write(LATTIMEREG, MLTIM(setup->master_latency_timer));

8
arch/mips/vr41xx/common/bcu.c
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@ -70,7 +70,7 @@ EXPORT_SYMBOL_GPL(vr41xx_get_tclock_frequency);
static inline uint16_t read_clkspeed(void)
{
switch (current_cpu_data.cputype) {
switch (current_cpu_type()) {
case CPU_VR4111:
case CPU_VR4121: return readw(CLKSPEEDREG_TYPE1);
case CPU_VR4122:
@ -88,7 +88,7 @@ static inline unsigned long calculate_pclock(uint16_t clkspeed)
{
unsigned long pclock = 0;
switch (current_cpu_data.cputype) {
switch (current_cpu_type()) {
case CPU_VR4111:
case CPU_VR4121:
pclock = 18432000 * 64;
@ -138,7 +138,7 @@ static inline unsigned long calculate_vtclock(uint16_t clkspeed, unsigned long p
{
unsigned long vtclock = 0;
switch (current_cpu_data.cputype) {
switch (current_cpu_type()) {
case CPU_VR4111:
/* The NEC VR4111 doesn't have the VTClock. */
break;
@ -180,7 +180,7 @@ static inline unsigned long calculate_tclock(uint16_t clkspeed, unsigned long pc
{
unsigned long tclock = 0;
switch (current_cpu_data.cputype) {
switch (current_cpu_type()) {
case CPU_VR4111:
if (!(clkspeed & DIV2B))
tclock = pclock / 2;

16
arch/mips/vr41xx/common/cmu.c
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@ -95,8 +95,8 @@ void vr41xx_supply_clock(vr41xx_clock_t clock)
cmuclkmsk |= MSKFIR | MSKFFIR;
break;
case DSIU_CLOCK:
if (current_cpu_data.cputype == CPU_VR4111 ||
current_cpu_data.cputype == CPU_VR4121)
if (current_cpu_type() == CPU_VR4111 ||
current_cpu_type() == CPU_VR4121)
cmuclkmsk |= MSKDSIU;
else
cmuclkmsk |= MSKSIU | MSKDSIU;
@ -146,8 +146,8 @@ void vr41xx_mask_clock(vr41xx_clock_t clock)
cmuclkmsk &= ~MSKPIU;
break;
case SIU_CLOCK:
if (current_cpu_data.cputype == CPU_VR4111 ||
current_cpu_data.cputype == CPU_VR4121) {
if (current_cpu_type() == CPU_VR4111 ||
current_cpu_type() == CPU_VR4121) {
cmuclkmsk &= ~(MSKSIU | MSKSSIU);
} else {
if (cmuclkmsk & MSKDSIU)
@ -166,8 +166,8 @@ void vr41xx_mask_clock(vr41xx_clock_t clock)
cmuclkmsk &= ~(MSKFIR | MSKFFIR);
break;
case DSIU_CLOCK:
if (current_cpu_data.cputype == CPU_VR4111 ||
current_cpu_data.cputype == CPU_VR4121) {
if (current_cpu_type() == CPU_VR4111 ||
current_cpu_type() == CPU_VR4121) {
cmuclkmsk &= ~MSKDSIU;
} else {
if (cmuclkmsk & MSKSSIU)
@ -216,7 +216,7 @@ static int __init vr41xx_cmu_init(void)
{
unsigned long start, size;
switch (current_cpu_data.cputype) {
switch (current_cpu_type()) {
case CPU_VR4111:
case CPU_VR4121:
start = CMU_TYPE1_BASE;
@ -246,7 +246,7 @@ static int __init vr41xx_cmu_init(void)
}
cmuclkmsk = cmu_read(CMUCLKMSK);
if (current_cpu_data.cputype == CPU_VR4133)
if (current_cpu_type() == CPU_VR4133)
cmuclkmsk2 = cmu_read(CMUCLKMSK2);
spin_lock_init(&cmu_lock);

2
arch/mips/vr41xx/common/giu.c
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@ -81,7 +81,7 @@ static int __init vr41xx_giu_add(void)
if (!pdev)
return -ENOMEM;
switch (current_cpu_data.cputype) {
switch (current_cpu_type()) {
case CPU_VR4111:
case CPU_VR4121:
pdev->id = GPIO_50PINS_PULLUPDOWN;

76
arch/mips/vr41xx/common/icu.c
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@ -157,8 +157,8 @@ void vr41xx_enable_piuint(uint16_t mask)
struct irq_desc *desc = irq_desc + PIU_IRQ;
unsigned long flags;
if (current_cpu_data.cputype == CPU_VR4111 ||
current_cpu_data.cputype == CPU_VR4121) {
if (current_cpu_type() == CPU_VR4111 ||
current_cpu_type() == CPU_VR4121) {
spin_lock_irqsave(&desc->lock, flags);
icu1_set(MPIUINTREG, mask);
spin_unlock_irqrestore(&desc->lock, flags);
@ -172,8 +172,8 @@ void vr41xx_disable_piuint(uint16_t mask)
struct irq_desc *desc = irq_desc + PIU_IRQ;
unsigned long flags;
if (current_cpu_data.cputype == CPU_VR4111 ||
current_cpu_data.cputype == CPU_VR4121) {
if (current_cpu_type() == CPU_VR4111 ||
current_cpu_type() == CPU_VR4121) {
spin_lock_irqsave(&desc->lock, flags);
icu1_clear(MPIUINTREG, mask);
spin_unlock_irqrestore(&desc->lock, flags);
@ -187,8 +187,8 @@ void vr41xx_enable_aiuint(uint16_t mask)
struct irq_desc *desc = irq_desc + AIU_IRQ;
unsigned long flags;
if (current_cpu_data.cputype == CPU_VR4111 ||
current_cpu_data.cputype == CPU_VR4121) {
if (current_cpu_type() == CPU_VR4111 ||
current_cpu_type() == CPU_VR4121) {
spin_lock_irqsave(&desc->lock, flags);
icu1_set(MAIUINTREG, mask);
spin_unlock_irqrestore(&desc->lock, flags);
@ -202,8 +202,8 @@ void vr41xx_disable_aiuint(uint16_t mask)
struct irq_desc *desc = irq_desc + AIU_IRQ;
unsigned long flags;
if (current_cpu_data.cputype == CPU_VR4111 ||
current_cpu_data.cputype == CPU_VR4121) {
if (current_cpu_type() == CPU_VR4111 ||
current_cpu_type() == CPU_VR4121) {
spin_lock_irqsave(&desc->lock, flags);
icu1_clear(MAIUINTREG, mask);
spin_unlock_irqrestore(&desc->lock, flags);
@ -217,8 +217,8 @@ void vr41xx_enable_kiuint(uint16_t mask)
struct irq_desc *desc = irq_desc + KIU_IRQ;
unsigned long flags;
if (current_cpu_data.cputype == CPU_VR4111 ||
current_cpu_data.cputype == CPU_VR4121) {
if (current_cpu_type() == CPU_VR4111 ||
current_cpu_type() == CPU_VR4121) {
spin_lock_irqsave(&desc->lock, flags);
icu1_set(MKIUINTREG, mask);
spin_unlock_irqrestore(&desc->lock, flags);
@ -232,8 +232,8 @@ void vr41xx_disable_kiuint(uint16_t mask)
struct irq_desc *desc = irq_desc + KIU_IRQ;
unsigned long flags;
if (current_cpu_data.cputype == CPU_VR4111 ||
current_cpu_data.cputype == CPU_VR4121) {
if (current_cpu_type() == CPU_VR4111 ||
current_cpu_type() == CPU_VR4121) {
spin_lock_irqsave(&desc->lock, flags);
icu1_clear(MKIUINTREG, mask);
spin_unlock_irqrestore(&desc->lock, flags);
@ -319,9 +319,9 @@ void vr41xx_enable_pciint(void)
struct irq_desc *desc = irq_desc + PCI_IRQ;
unsigned long flags;
if (current_cpu_data.cputype == CPU_VR4122 ||
current_cpu_data.cputype == CPU_VR4131 ||
current_cpu_data.cputype == CPU_VR4133) {
if (current_cpu_type() == CPU_VR4122 ||
current_cpu_type() == CPU_VR4131 ||
current_cpu_type() == CPU_VR4133) {
spin_lock_irqsave(&desc->lock, flags);
icu2_write(MPCIINTREG, PCIINT0);
spin_unlock_irqrestore(&desc->lock, flags);
@ -335,9 +335,9 @@ void vr41xx_disable_pciint(void)
struct irq_desc *desc = irq_desc + PCI_IRQ;
unsigned long flags;
if (current_cpu_data.cputype == CPU_VR4122 ||
current_cpu_data.cputype == CPU_VR4131 ||
current_cpu_data.cputype == CPU_VR4133) {
if (current_cpu_type() == CPU_VR4122 ||
current_cpu_type() == CPU_VR4131 ||
current_cpu_type() == CPU_VR4133) {
spin_lock_irqsave(&desc->lock, flags);
icu2_write(MPCIINTREG, 0);
spin_unlock_irqrestore(&desc->lock, flags);
@ -351,9 +351,9 @@ void vr41xx_enable_scuint(void)
struct irq_desc *desc = irq_desc + SCU_IRQ;
unsigned long flags;
if (current_cpu_data.cputype == CPU_VR4122 ||
current_cpu_data.cputype == CPU_VR4131 ||
current_cpu_data.cputype == CPU_VR4133) {
if (current_cpu_type() == CPU_VR4122 ||
current_cpu_type() == CPU_VR4131 ||
current_cpu_type() == CPU_VR4133) {
spin_lock_irqsave(&desc->lock, flags);
icu2_write(MSCUINTREG, SCUINT0);
spin_unlock_irqrestore(&desc->lock, flags);
@ -367,9 +367,9 @@ void vr41xx_disable_scuint(void)
struct irq_desc *desc = irq_desc + SCU_IRQ;
unsigned long flags;
if (current_cpu_data.cputype == CPU_VR4122 ||
current_cpu_data.cputype == CPU_VR4131 ||
current_cpu_data.cputype == CPU_VR4133) {
if (current_cpu_type() == CPU_VR4122 ||
current_cpu_type() == CPU_VR4131 ||
current_cpu_type() == CPU_VR4133) {
spin_lock_irqsave(&desc->lock, flags);
icu2_write(MSCUINTREG, 0);
spin_unlock_irqrestore(&desc->lock, flags);
@ -383,9 +383,9 @@ void vr41xx_enable_csiint(uint16_t mask)
struct irq_desc *desc = irq_desc + CSI_IRQ;
unsigned long flags;
if (current_cpu_data.cputype == CPU_VR4122 ||
current_cpu_data.cputype == CPU_VR4131 ||
current_cpu_data.cputype == CPU_VR4133) {
if (current_cpu_type() == CPU_VR4122 ||
current_cpu_type() == CPU_VR4131 ||
current_cpu_type() == CPU_VR4133) {
spin_lock_irqsave(&desc->lock, flags);
icu2_set(MCSIINTREG, mask);
spin_unlock_irqrestore(&desc->lock, flags);
@ -399,9 +399,9 @@ void vr41xx_disable_csiint(uint16_t mask)
struct irq_desc *desc = irq_desc + CSI_IRQ;
unsigned long flags;
if (current_cpu_data.cputype == CPU_VR4122 ||
current_cpu_data.cputype == CPU_VR4131 ||
current_cpu_data.cputype == CPU_VR4133) {
if (current_cpu_type() == CPU_VR4122 ||
current_cpu_type() == CPU_VR4131 ||
current_cpu_type() == CPU_VR4133) {
spin_lock_irqsave(&desc->lock, flags);
icu2_clear(MCSIINTREG, mask);
spin_unlock_irqrestore(&desc->lock, flags);
@ -415,9 +415,9 @@ void vr41xx_enable_bcuint(void)
struct irq_desc *desc = irq_desc + BCU_IRQ;
unsigned long flags;
if (current_cpu_data.cputype == CPU_VR4122 ||
current_cpu_data.cputype == CPU_VR4131 ||
current_cpu_data.cputype == CPU_VR4133) {
if (current_cpu_type() == CPU_VR4122 ||
current_cpu_type() == CPU_VR4131 ||
current_cpu_type() == CPU_VR4133) {
spin_lock_irqsave(&desc->lock, flags);
icu2_write(MBCUINTREG, BCUINTR);
spin_unlock_irqrestore(&desc->lock, flags);
@ -431,9 +431,9 @@ void vr41xx_disable_bcuint(void)
struct irq_desc *desc = irq_desc + BCU_IRQ;
unsigned long flags;
if (current_cpu_data.cputype == CPU_VR4122 ||
current_cpu_data.cputype == CPU_VR4131 ||
current_cpu_data.cputype == CPU_VR4133) {
if (current_cpu_type() == CPU_VR4122 ||
current_cpu_type() == CPU_VR4131 ||
current_cpu_type() == CPU_VR4133) {
spin_lock_irqsave(&desc->lock, flags);
icu2_write(MBCUINTREG, 0);
spin_unlock_irqrestore(&desc->lock, flags);
@ -608,7 +608,7 @@ int vr41xx_set_intassign(unsigned int irq, unsigned char intassign)
{
int retval = -EINVAL;
if (current_cpu_data.cputype != CPU_VR4133)
if (current_cpu_type() != CPU_VR4133)
return -EINVAL;
if (intassign > INTASSIGN_MAX)
@ -665,7 +665,7 @@ static int __init vr41xx_icu_init(void)
unsigned long icu1_start, icu2_start;
int i;
switch (current_cpu_data.cputype) {
switch (current_cpu_type()) {
case CPU_VR4111:
case CPU_VR4121:
icu1_start = ICU1_TYPE1_BASE;

4
arch/mips/vr41xx/common/pmu.c
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@ -62,7 +62,7 @@ static inline void software_reset(void)
{
uint16_t pmucnt2;
switch (current_cpu_data.cputype) {
switch (current_cpu_type()) {
case CPU_VR4122:
case CPU_VR4131:
case CPU_VR4133:
@ -98,7 +98,7 @@ static int __init vr41xx_pmu_init(void)
{
unsigned long start, size;
switch (current_cpu_data.cputype) {
switch (current_cpu_type()) {
case CPU_VR4111:
case CPU_VR4121:
start = PMU_TYPE1_BASE;

2
arch/mips/vr41xx/common/rtc.c
Unescape View File

@ -82,7 +82,7 @@ static int __init vr41xx_rtc_add(void)
if (!pdev)
return -ENOMEM;
switch (current_cpu_data.cputype) {
switch (current_cpu_type()) {
case CPU_VR4111:
case CPU_VR4121:
res = rtc_type1_resource;

2
arch/mips/vr41xx/common/siu.c
Unescape View File

@ -83,7 +83,7 @@ static int __init vr41xx_siu_add(void)
if (!pdev)
return -ENOMEM;
switch (current_cpu_data.cputype) {
switch (current_cpu_type()) {
case CPU_VR4111:
case CPU_VR4121:
pdev->dev.platform_data = siu_type1_ports;

5
include/asm-mips/cpu-features.h
Unescape View File

@ -9,11 +9,14 @@
#ifndef __ASM_CPU_FEATURES_H
#define __ASM_CPU_FEATURES_H
#include <asm/cpu.h>
#include <asm/cpu-info.h>
#include <cpu-feature-overrides.h>
#ifndef current_cpu_type
#define current_cpu_type() current_cpu_data.cputype
#endif
/*
* SMP assumption: Options of CPU 0 are a superset of all processors.
* This is true for all known MIPS systems.

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