Removed mac addr entry in dtsi file in order to
generate random mac addr.
Change-Id: Ibfe7a76953d9ff6eec75a1d13323d7d92a530083
Signed-off-by: Karthik Rudrapatna <krudrapa@codeaurora.org>
Override mtl_rx_setup and mtl_tx_setup for cv2x.
Add qoe_mode and and qoe vlan filtering config.
Add cv2x_mode AP and cv2x vlan filtering config.
Change-Id: I4e2e466ea6a547894695483508ab286bcfa69626
Acked-by: Ning Cai <ncai@qti.qualcomm.com>
Signed-off-by: Sunil Paidimarri <hisunil@codeaurora.org>
Change num of tx queues supported to 4 on emac.
Change-Id: Ie67040f5bdda03954299ed7bd489e0cdc60700bc
Acked-by: Ning Cai <ncai@qti.qualcomm.com>
Signed-off-by: Sunil Paidimarri <hisunil@codeaurora.org>
Add entry in devicetree for qrtr ethernet driver for sa2150p
target.
Change-Id: I85aa038202e9466ce427815d7d582c06125e481e
Signed-off-by: Jay Jayanna <jayanna@codeaurora.org>
Update ab votes for AXI bus to support bi-directional data rates.
Change-Id: If50906e88c00d469da7d976904c61e1d790d9749
Signed-off-by: Lakshit Tyagi <ltyagi@codeaurora.org>
Add dt entry to to enable geometry mapping for fastmap to save memory
Change-Id: I4811557ebd5f60b342000164277d2dd73813be79
Signed-off-by: Sneh Shah <snehshah@codeaurora.org>
QCS405 and SA2150P are quad core while QCS403 and SA2145P are
dual core. There are separate device tree files for quad and
dual core SoCs hence remove msm-id for dual core from quad
core dtsi include file.
Change-Id: I708a942076ebcfbcde2a4786175fb7a6166c23b5
Signed-off-by: Rishi Gupta <rishgupt@codeaurora.org>
Modify the pwm device node name for all pwm instances
for QCS405.
Change-Id: I120d232b941e12c30ce3fa2fe53961676ddda212
Signed-off-by: Saurabh Sahu <sausah@codeaurora.org>
disable i2c_2 and smp2p so that avoid error log.
Change-Id: I3b15fd732d93033df37b9b4250e37b4d4b88bce1
Signed-off-by: zhaochen <zhaochen@codeaurora.org>
Increase "cdsp_fw_mem" size to 8MB from 6MB for
QCS405/QCS403.
Change-Id: I4106c1b1ac5f34b297df2ce5cf41657b52763566
Signed-off-by: Vishwanath Raju K <vishk@codeaurora.org>
C404 Carrier board VBUS out supply by a single LDO module, which
control by GPIO-37.
Change-Id: I05cce17f8dc39edd09e8d1586db5517330672b6d
Signed-off-by: Chaojun Wang <chaojun@codeaurora.org>
C404 Carrier board VBUS out supply by a single LDO module, which
control by GPIO-37.
Change-Id: Ie54bfa04a045d0bb66e18df5d364dbd817fa9984
Signed-off-by: Chaojun Wang <chaojun@codeaurora.org>
There is conflict on the gpio 116 with USB part. Change to 109 for sku1
boards, change to 47 for sku4 boards. Revert SD card settings in main dtsi
for sdhc_2 slot.
Change-Id: I7c165f274244150404a371047602ab3d47567283
CRs-Fixed: 2555123
Signed-off-by: Hangtian Zhu <hangtian@codeaurora.org>
Fill correct reserved mem address for various subsystem.
Change-Id: I38e9ac4a828b701053edbb1822f278298be43a38
Signed-off-by: Govind Singh <govinds@codeaurora.org>
Set sdc2_wlan_on sdc2_wlan_off in main dtsi for QCS405. Observed some
SOM cards pulled up sdc2_wlan_on gpio later than sdio cmd sent,
which leads to card detect failure. Move this settings to main sdhc_2.
Change-Id: Ib9f0b5631b9f32a71437a6c20f29a6b2a9a63fdb
CRs-Fixed: 2545558
Signed-off-by: Hangtian Zhu <hangtian@codeaurora.org>
This change is to revert commit 0448c578ff ("ARM: dts: msm:
Update sdhc_2 settings for QCS405") qcs405-pinctrl change,
which involved mute button does not work issue. Will raise
wlan_en related changes for sdio wlan later after gpio
conflict is resolved.
Change-Id: Ic7983c0a8510ff5abc1eb33572204cf54364d093
CRs-Fixed: 2522568
Signed-off-by: Hangtian Zhu <hangtian@codeaurora.org>
SR PLL is connected to LDO3 so GPLL6 should vote for this
rail when there is a frequency request. Add support for
voting for this rail.
Change-Id: Icb8c79b5668ca9571002092746824a55cb650a33
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Update sdhc_2 settings for QCS405 to support new second radio.
SDIO clock 100 MHz, mmc bootup delay 100 ms before issuing CMD5.
vdd-io supply is l6.
Change-Id: Icf9bbe44294288f72ee9e2ad4c566e034743eff3
CRs-Fixed: 2515164
Signed-off-by: Hangtian Zhu <hangtian@codeaurora.org>
This reverts commit 1b42f34190.
RPM changes are needed before this one.
Change-Id: I86f8c5a92d2772603630ca80a9b87d2f30793ce9
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The new timer wheel avoid cascading down the timers, this comes
on relaxed granularity and for in place expiry of timers.
Adjust pet timer granularity accorddingly.
Change-Id: I3488a129741b4ad21a48714294bb54c2ded003db
Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>
SR PLL is connected to LDO3 so GPLL6 should vote for this
rail when there is a frequency request. Add support for
voting for this rail.
Change-Id: I264daffb2de2b6461e2fdbced96454a21ec29a12
Signed-off-by: Shefali Jain <shefjain@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Remove the MHI device tree file and references since
it will be provided by EAP kernel bundle.
Change-Id: Id53f49302d22060de9acbd7dce6b1c503da278f1
Signed-off-by: Gustavo Solaira <gustavos@codeaurora.org>
Add cnss_sdio dt for QCS405 and enable sdio in sdhc_2 for 2nd wifi with
sdio interface.
Change-Id: Iaee42a97fed487c099b6578c0decd0ad629c1e1d
CRs-Fixed: 2487180
Signed-off-by: hangtian <hangtian@codeaurora.org>
Add initial devicetree node to support MHI based devices
over PCIe on QCS405.
Change-Id: I609a4d22303db37555f0ad323649516ac823160a
Signed-off-by: Rama Krishna Phani A <rphani@codeaurora.org>
Increase "wlan_fw_mem" pil size to 16MB from 15MB for
QCS405/QCS403.
Change-Id: Ib48ef2f02b882a16e8865b11b27c4fb125ab3778
Signed-off-by: Vishwanath Raju K <vishk@codeaurora.org>
Add MSM PCIe bus driver device nodes in main and pinctrl
devicetree for QCS405 to enable communication between QCS405
and external peripherals connected via PCIe in RC mode.
Change-Id: I06fd890bf3dc84828dc37853ac274ee01018eb6b
Signed-off-by: Rama Krishna Phani A <rphani@codeaurora.org>
Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>
Reduced adsp pil size to 20MB and 18MB from 26MB for QCS405
and QCS403 respectively.
Change-Id: I7ced0270e584c52ae7673a54d1de684ca380d4f3
Signed-off-by: Vishwanath Raju K <vishk@codeaurora.org>
The apps region notification call is wrappered with
the above property only. The TZ apps region notification
call will be only sent to TZ from HLOS only when
appsbl-qseecom-support property is not defined in the qseecom
node.
Change-Id: Id8cd35d1a236dd1c71c1ca3ad6286c8f91f75f42
Signed-off-by: Jiten Patel <jitepate@codeaurora.org>
Add qcedev and qcrypto device nodes to enable HW
crypto engine operations for user and kernel space
apps.
Change-Id: Ic9fb0ec86a207c0206e2cb0f2beeb28eecb4adf8
Signed-off-by: Jiten Patel <jitepate@codeaurora.org>
Reduced default,cma size to 4MB from 16MB for qcs403.
Change-Id: I54c14982cadaffd060bec12b47cf090307c7bfd5
Signed-off-by: Vishwanath Raju K <vishk@codeaurora.org>
update DDR IB value with proper width value for all the frequency
on qcs405 and qcs403 target.
Change-Id: Ibadced248850396bb95d7af2bbed980130812847
Signed-off-by: Santosh Mardi <gsantosh@codeaurora.org>
Disable DCC clocks during DCC is probing. It's for
fixing its abnormal reset.
Change-Id: I87535063089d6a95bb07bbf131b37a1e13130721
Signed-off-by: Jinfa Wang <jinfaw@codeaurora.org>
This change updates sdhc2 vdd-io voltage regulator(L11)
range to support UHS SD cards which requires voltage
switching to 1.8V.
Change-Id: I4a9fa184f275ec389d75aa209c62d3605bb1ab15
Signed-off-by: Sayali Lokhande <sayalil@codeaurora.org>
Add the smcinvoke dt node to communicate with TZ
from HLOS for qcs405 target.
Change-Id: Iab36b81ebc50f419e272111e15692a49f2579d12
Signed-off-by: Mohamed Sunfeer <msunfeer@codeaurora.org>
Increase the TZ apps region size to 5mb for qcs405 target.
Change-Id: I45df55c7d92ad29007783b3372812b5dd65cf718
Signed-off-by: Mohamed Sunfeer <msunfeer@codeaurora.org>
Increase MDF shared memory to 8MB to accommodate all the MDF
requirements.
Change-Id: I64047df228627dece6dc28890198152352948c73
Signed-off-by: Mangesh Kunchamwar <mangeshk@codeaurora.org>
Update PCA9956B LED node in QCS405 different for
circular mic array board and linear mic array board.
Change-Id: I7369c4d845ad8aad6db5b6b4fe9cf9d27a56fce2
Signed-off-by: Prashanth Vadde <pvadde@codeaurora.org>
Simon1511