clk: qcom: gcc-qcs405: Add support for vdd_sr_pll regulator

SR PLL is connected to LDO3 so GPLL6 should vote for this
rail when there is a frequency request. Add support for
voting for this rail.

Change-Id: I264daffb2de2b6461e2fdbced96454a21ec29a12
Signed-off-by: Shefali Jain <shefjain@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>

arch/arm64/boot/dts/qcom/qcs405.dtsi

@@ -310,6 +310,7 @@
 		reg = <0x1800000 0x80000>;
 		reg-names = "cc_base";
 		vdd_cx-supply = <&pms405_s1_level>;
+		vdd_sr_pll-supply = <&pms405_l3>;
 		clocks = <&clock_rpmcc RPM_SMD_XO_CLK_SRC>;
 		qcom,gcc_oxili_gfx3d_clk-opp-handle = <&msm_gpu>;
 		clock-names = "cxo";

drivers/clk/qcom/gcc-qcs405.c

@@ -41,6 +41,7 @@
 #define F_SLEW(f, s, h, m, n, sf) { (f), (s), (2 * (h) - 1), (m), (n), (sf) }
 
 static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner);
+static DEFINE_VDD_REGULATORS(vdd_sr_pll, VDD_SR_PLL_NUM, 1, vdd_sr_levels);
 
 enum {
 	P_CORE_BI_PLL_TEST_SE,
@@ -412,6 +413,11 @@ static struct clk_pll gpll6 = {
 		.parent_names = (const char *[]){ "cxo" },
 		.num_parents = 1,
 		.ops = &clk_pll_ops,
+		.vdd_class = &vdd_sr_pll,
+		.rate_max = (unsigned long [VDD_SR_PLL_NUM]) {
+			[VDD_SR_PLL_SVS] = 1080000000,
+		},
+		.num_rate_max = VDD_SR_PLL_NUM,
 	},
 };
 
@@ -2957,6 +2963,14 @@ static int gcc_qcs405_probe(struct platform_device *pdev)
 		return PTR_ERR(vdd_cx.regulator[0]);
 	}
 
+	vdd_sr_pll.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_sr_pll");
+	if (IS_ERR(vdd_sr_pll.regulator[0])) {
+		if (!(PTR_ERR(vdd_sr_pll.regulator[0]) == -EPROBE_DEFER))
+			dev_err(&pdev->dev,
+				"Unable to get vdd_sr_pll regulator\n");
+		return PTR_ERR(vdd_sr_pll.regulator[0]);
+	}
+
 	clk_alpha_pll_configure(&gpll3_out_main, regmap, &gpll3_config);
 
 	clk = devm_clk_register(&pdev->dev, &wcnss_m_clk.hw);

drivers/clk/qcom/vdd-level-405.h

@@ -55,4 +55,19 @@ static int vdd_hf_levels[] = {
 	1800000, RPM_REGULATOR_LEVEL_TURBO,	/* VDD_HF_PLL_TUR */
 };
 
+enum vdd_sr_pll_levels {
+	VDD_SR_PLL_OFF,
+	VDD_SR_PLL_SVS,
+	VDD_SR_PLL_NOM,
+	VDD_SR_PLL_TUR,
+	VDD_SR_PLL_NUM,
+};
+
+static int vdd_sr_levels[] = {
+	0,	/* VDD_SR_PLL_OFF */
+	976000,	/* VDD_SR_PLL_SVS */
+	976000,	/* VDD_SR_PLL_NOM */
+	976000,	/* VDD_SR_PLL_TUR */
+};
+
 #endif