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Merge branch 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm

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Pull ARM fixes from Russell King:
 "A number of low impact fixes, the most noticable one is the thumb2
  frame pointer fix.  We also fix a regression caused during this merge
  window with ARM925 CPUs running with caches disabled, and fix a number
  of warnings"

* 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
  ARM: arm925: ensure assembly sets up writethrough mapping
  ARM: perf: fix compiler warning with gcc 4.6.4 (and tidy code)
  ARM: l2c: fix dependencies on PL310 errata symbols
  ARM: 8069/1: Make thread_save_fp macro aware of THUMB2 mode
  ARM: 8068/1: scoop: Remove unused variable
tirimbino
Linus Torvalds 11 years ago
parent 8b8f5d9715 b8d8772e53
commit b4b664bef4
10 changed files with 25 additions and 20 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Show Stats Download Patch File Download Diff File
  1. 1
      arch/arm/common/scoop.c
  2. 6
      arch/arm/include/asm/thread_info.h
  3. 4
      arch/arm/kernel/perf_event_v7.c
  4. 12
      arch/arm/mach-imx/Kconfig
  5. 4
      arch/arm/mach-omap2/Kconfig
  6. 4
      arch/arm/mach-sti/Kconfig
  7. 2
      arch/arm/mach-ux500/Kconfig
  8. 2
      arch/arm/mach-vexpress/Kconfig
  9. 9
      arch/arm/mm/Kconfig
  10. 1
      arch/arm/mm/proc-arm925.S

1
arch/arm/common/scoop.c
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@ -182,7 +182,6 @@ static int scoop_probe(struct platform_device *pdev)
struct scoop_config *inf; struct scoop_config *inf;
struct resource *mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); struct resource *mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
int ret; int ret;
int temp;
if (!mem) if (!mem)
return -EINVAL; return -EINVAL;

6
arch/arm/include/asm/thread_info.h
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@ -114,8 +114,14 @@ static inline struct thread_info *current_thread_info(void)
((unsigned long)(task_thread_info(tsk)->cpu_context.pc)) ((unsigned long)(task_thread_info(tsk)->cpu_context.pc))
#define thread_saved_sp(tsk) \ #define thread_saved_sp(tsk) \
((unsigned long)(task_thread_info(tsk)->cpu_context.sp)) ((unsigned long)(task_thread_info(tsk)->cpu_context.sp))
#ifndef CONFIG_THUMB2_KERNEL
#define thread_saved_fp(tsk) \ #define thread_saved_fp(tsk) \
((unsigned long)(task_thread_info(tsk)->cpu_context.fp)) ((unsigned long)(task_thread_info(tsk)->cpu_context.fp))
#else
#define thread_saved_fp(tsk) \
((unsigned long)(task_thread_info(tsk)->cpu_context.r7))
#endif
extern void crunch_task_disable(struct thread_info *); extern void crunch_task_disable(struct thread_info *);
extern void crunch_task_copy(struct thread_info *, void *); extern void crunch_task_copy(struct thread_info *, void *);

4
arch/arm/kernel/perf_event_v7.c
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@ -1924,7 +1924,7 @@ static int krait_pmu_get_event_idx(struct pmu_hw_events *cpuc,
struct perf_event *event) struct perf_event *event)
{ {
int idx; int idx;
int bit; int bit = -1;
unsigned int prefix; unsigned int prefix;
unsigned int region; unsigned int region;
unsigned int code; unsigned int code;
@ -1953,7 +1953,7 @@ static int krait_pmu_get_event_idx(struct pmu_hw_events *cpuc,
} }
idx = armv7pmu_get_event_idx(cpuc, event); idx = armv7pmu_get_event_idx(cpuc, event);
if (idx < 0 && krait_event) if (idx < 0 && bit >= 0)
clear_bit(bit, cpuc->used_mask); clear_bit(bit, cpuc->used_mask);
return idx; return idx;

12
arch/arm/mach-imx/Kconfig
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@ -734,9 +734,9 @@ config SOC_IMX6
select HAVE_IMX_MMDC select HAVE_IMX_MMDC
select HAVE_IMX_SRC select HAVE_IMX_SRC
select MFD_SYSCON select MFD_SYSCON
select PL310_ERRATA_588369 if CACHE_PL310 select PL310_ERRATA_588369 if CACHE_L2X0
select PL310_ERRATA_727915 if CACHE_PL310 select PL310_ERRATA_727915 if CACHE_L2X0
select PL310_ERRATA_769419 if CACHE_PL310 select PL310_ERRATA_769419 if CACHE_L2X0
config SOC_IMX6Q config SOC_IMX6Q
bool "i.MX6 Quad/DualLite support" bool "i.MX6 Quad/DualLite support"
@ -771,9 +771,9 @@ config SOC_VF610
select ARM_GIC select ARM_GIC
select PINCTRL_VF610 select PINCTRL_VF610
select VF_PIT_TIMER select VF_PIT_TIMER
select PL310_ERRATA_588369 if CACHE_PL310 select PL310_ERRATA_588369 if CACHE_L2X0
select PL310_ERRATA_727915 if CACHE_PL310 select PL310_ERRATA_727915 if CACHE_L2X0
select PL310_ERRATA_769419 if CACHE_PL310 select PL310_ERRATA_769419 if CACHE_L2X0
help help
This enable support for Freescale Vybrid VF610 processor. This enable support for Freescale Vybrid VF610 processor.

4
arch/arm/mach-omap2/Kconfig
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@ -34,8 +34,8 @@ config ARCH_OMAP4
select HAVE_ARM_SCU if SMP select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP select HAVE_ARM_TWD if SMP
select OMAP_INTERCONNECT select OMAP_INTERCONNECT
select PL310_ERRATA_588369 select PL310_ERRATA_588369 if CACHE_L2X0
select PL310_ERRATA_727915 select PL310_ERRATA_727915 if CACHE_L2X0
select PM_OPP if PM select PM_OPP if PM
select PM_RUNTIME if CPU_IDLE select PM_RUNTIME if CPU_IDLE
select ARM_ERRATA_754322 select ARM_ERRATA_754322

4
arch/arm/mach-sti/Kconfig
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@ -11,8 +11,8 @@ menuconfig ARCH_STI
select ARM_ERRATA_754322 select ARM_ERRATA_754322
select ARM_ERRATA_764369 if SMP select ARM_ERRATA_764369 if SMP
select ARM_ERRATA_775420 select ARM_ERRATA_775420
select PL310_ERRATA_753970 if CACHE_PL310 select PL310_ERRATA_753970 if CACHE_L2X0
select PL310_ERRATA_769419 if CACHE_PL310 select PL310_ERRATA_769419 if CACHE_L2X0
help help
Include support for STiH41x SOCs like STiH415/416 using the device tree Include support for STiH41x SOCs like STiH415/416 using the device tree
for discovery for discovery

2
arch/arm/mach-ux500/Kconfig
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@ -15,7 +15,7 @@ menuconfig ARCH_U8500
select PINCTRL select PINCTRL
select PINCTRL_ABX500 select PINCTRL_ABX500
select PINCTRL_NOMADIK select PINCTRL_NOMADIK
select PL310_ERRATA_753970 if CACHE_PL310 select PL310_ERRATA_753970 if CACHE_L2X0
help help
Support for ST-Ericsson's Ux500 architecture Support for ST-Ericsson's Ux500 architecture

2
arch/arm/mach-vexpress/Kconfig
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@ -43,7 +43,7 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
bool "Enable A5 and A9 only errata work-arounds" bool "Enable A5 and A9 only errata work-arounds"
default y default y
select ARM_ERRATA_720789 select ARM_ERRATA_720789
select PL310_ERRATA_753970 if CACHE_PL310 select PL310_ERRATA_753970 if CACHE_L2X0
help help
Provides common dependencies for Versatile Express platforms Provides common dependencies for Versatile Express platforms
based on Cortex-A5 and Cortex-A9 processors. In order to based on Cortex-A5 and Cortex-A9 processors. In order to

9
arch/arm/mm/Kconfig
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@ -889,9 +889,10 @@ config CACHE_L2X0
help help
This option enables the L2x0 PrimeCell. This option enables the L2x0 PrimeCell.
if CACHE_L2X0
config CACHE_PL310 config CACHE_PL310
bool bool
depends on CACHE_L2X0
default y if CPU_V7 && !(CPU_V6 || CPU_V6K) default y if CPU_V7 && !(CPU_V6 || CPU_V6K)
help help
This option enables optimisations for the PL310 cache This option enables optimisations for the PL310 cache
@ -899,7 +900,6 @@ config CACHE_PL310
config PL310_ERRATA_588369 config PL310_ERRATA_588369
bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
depends on CACHE_L2X0
help help
The PL310 L2 cache controller implements three types of Clean & The PL310 L2 cache controller implements three types of Clean &
Invalidate maintenance operations: by Physical Address Invalidate maintenance operations: by Physical Address
@ -912,7 +912,6 @@ config PL310_ERRATA_588369
config PL310_ERRATA_727915 config PL310_ERRATA_727915
bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
depends on CACHE_L2X0
help help
PL310 implements the Clean & Invalidate by Way L2 cache maintenance PL310 implements the Clean & Invalidate by Way L2 cache maintenance
operation (offset 0x7FC). This operation runs in background so that operation (offset 0x7FC). This operation runs in background so that
@ -923,7 +922,6 @@ config PL310_ERRATA_727915
config PL310_ERRATA_753970 config PL310_ERRATA_753970
bool "PL310 errata: cache sync operation may be faulty" bool "PL310 errata: cache sync operation may be faulty"
depends on CACHE_PL310
help help
This option enables the workaround for the 753970 PL310 (r3p0) erratum. This option enables the workaround for the 753970 PL310 (r3p0) erratum.
@ -938,7 +936,6 @@ config PL310_ERRATA_753970
config PL310_ERRATA_769419 config PL310_ERRATA_769419
bool "PL310 errata: no automatic Store Buffer drain" bool "PL310 errata: no automatic Store Buffer drain"
depends on CACHE_L2X0
help help
On revisions of the PL310 prior to r3p2, the Store Buffer does On revisions of the PL310 prior to r3p2, the Store Buffer does
not automatically drain. This can cause normal, non-cacheable not automatically drain. This can cause normal, non-cacheable
@ -948,6 +945,8 @@ config PL310_ERRATA_769419
on systems with an outer cache, the store buffer is drained on systems with an outer cache, the store buffer is drained
explicitly. explicitly.
endif
config CACHE_TAUROS2 config CACHE_TAUROS2
bool "Enable the Tauros2 L2 cache controller" bool "Enable the Tauros2 L2 cache controller"
depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4) depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)

1
arch/arm/mm/proc-arm925.S
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@ -502,6 +502,7 @@ __\name\()_proc_info:
.long \cpu_val .long \cpu_val
.long \cpu_mask .long \cpu_mask
.long PMD_TYPE_SECT | \ .long PMD_TYPE_SECT | \
PMD_SECT_CACHEABLE | \
PMD_BIT4 | \ PMD_BIT4 | \
PMD_SECT_AP_WRITE | \ PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ PMD_SECT_AP_READ

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