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Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

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Pull drm fixes from Dave Airlie:
 "A bunch of fixes for radeon, intel, omap and one amdkfd fix.

  Radeon fixes are all over, but it does fix some cursor corruption
  across suspend/resume.  i915 should fix the second warn you were
  seeing, so let us know if not.  omap is a bunch of small fixes"

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (28 commits)
  drm/radeon: disable vce init on cayman (v2)
  drm/amdgpu: fix timeout calculation
  drm/radeon: check if BO_VA is set before adding it to the invalidation list
  drm/radeon: allways add the VM clear duplicate
  Revert "Revert "drm/radeon: dont switch vt on suspend""
  drm/radeon: Fold radeon_set_cursor() into radeon_show_cursor()
  drm/radeon: unpin cursor BOs on suspend and pin them again on resume (v2)
  drm/radeon: Clean up reference counting and pinning of the cursor BOs
  drm/amdkfd: validate pdd where it acquired first
  Revert "drm/i915: Allocate context objects from stolen"
  drm/i915: Declare the swizzling unknown for L-shaped configurations
  drm/radeon: fix underflow in r600_cp_dispatch_texture()
  drm/radeon: default to 2048 MB GART size on SI+
  drm/radeon: fix HDP flushing
  drm/radeon: use RCU query for GEM_BUSY syscall
  drm/amdgpu: Handle irqs only based on irq ring, not irq status regs.
  drm/radeon: Handle irqs only based on irq ring, not irq status regs.
  drm/i915: Use crtc_state->active in primary check_plane func
  drm/i915: Check crtc->active in intel_crtc_disable_planes
  drm/i915: Restore all GGTT VMAs on resume
  ...
tirimbino
Linus Torvalds 10 years ago
parent 2278cb0bb3 2d28b633c3
commit 9cb1680c20
27 changed files with 964 additions and 717 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 2
      drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
  2. 22
      drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
  3. 22
      drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
  4. 22
      drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
  5. 9
      drivers/gpu/drm/amd/amdkfd/kfd_process.c
  6. 4
      drivers/gpu/drm/i915/i915_gem_context.c
  7. 23
      drivers/gpu/drm/i915/i915_gem_gtt.c
  8. 12
      drivers/gpu/drm/i915/i915_gem_tiling.c
  9. 12
      drivers/gpu/drm/i915/intel_display.c
  10. 2
      drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
  11. 6
      drivers/gpu/drm/omapdrm/omap_drv.h
  12. 16
      drivers/gpu/drm/omapdrm/omap_fb.c
  13. 2
      drivers/gpu/drm/omapdrm/omap_fbdev.c
  14. 26
      drivers/gpu/drm/omapdrm/omap_gem.c
  15. 26
      drivers/gpu/drm/omapdrm/omap_plane.c
  16. 336
      drivers/gpu/drm/radeon/cik.c
  17. 392
      drivers/gpu/drm/radeon/evergreen.c
  18. 25
      drivers/gpu/drm/radeon/ni.c
  19. 155
      drivers/gpu/drm/radeon/r600.c
  20. 2
      drivers/gpu/drm/radeon/r600_cp.c
  21. 109
      drivers/gpu/drm/radeon/radeon_cursor.c
  22. 66
      drivers/gpu/drm/radeon/radeon_device.c
  23. 1
      drivers/gpu/drm/radeon/radeon_fb.c
  24. 12
      drivers/gpu/drm/radeon/radeon_gem.c
  25. 1
      drivers/gpu/drm/radeon/radeon_mode.h
  26. 40
      drivers/gpu/drm/radeon/radeon_vm.c
  27. 336
      drivers/gpu/drm/radeon/si.c

2
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
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@ -352,7 +352,7 @@ unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
if (((int64_t)timeout_ns) < 0) if (((int64_t)timeout_ns) < 0)
return MAX_SCHEDULE_TIMEOUT; return MAX_SCHEDULE_TIMEOUT;
timeout = ktime_sub_ns(ktime_get(), timeout_ns); timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
if (ktime_to_ns(timeout) < 0) if (ktime_to_ns(timeout) < 0)
return 0; return 0;

22
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
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@ -3403,19 +3403,25 @@ static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
switch (entry->src_data) { switch (entry->src_data) {
case 0: /* vblank */ case 0: /* vblank */
if (disp_int & interrupt_status_offsets[crtc].vblank) { if (disp_int & interrupt_status_offsets[crtc].vblank)
dce_v10_0_crtc_vblank_int_ack(adev, crtc); dce_v10_0_crtc_vblank_int_ack(adev, crtc);
if (amdgpu_irq_enabled(adev, source, irq_type)) { else
drm_handle_vblank(adev->ddev, crtc); DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
}
DRM_DEBUG("IH: D%d vblank\n", crtc + 1); if (amdgpu_irq_enabled(adev, source, irq_type)) {
drm_handle_vblank(adev->ddev, crtc);
} }
DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
break; break;
case 1: /* vline */ case 1: /* vline */
if (disp_int & interrupt_status_offsets[crtc].vline) { if (disp_int & interrupt_status_offsets[crtc].vline)
dce_v10_0_crtc_vline_int_ack(adev, crtc); dce_v10_0_crtc_vline_int_ack(adev, crtc);
DRM_DEBUG("IH: D%d vline\n", crtc + 1); else
} DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
DRM_DEBUG("IH: D%d vline\n", crtc + 1);
break; break;
default: default:
DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);

22
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
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@ -3402,19 +3402,25 @@ static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
switch (entry->src_data) { switch (entry->src_data) {
case 0: /* vblank */ case 0: /* vblank */
if (disp_int & interrupt_status_offsets[crtc].vblank) { if (disp_int & interrupt_status_offsets[crtc].vblank)
dce_v11_0_crtc_vblank_int_ack(adev, crtc); dce_v11_0_crtc_vblank_int_ack(adev, crtc);
if (amdgpu_irq_enabled(adev, source, irq_type)) { else
drm_handle_vblank(adev->ddev, crtc); DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
}
DRM_DEBUG("IH: D%d vblank\n", crtc + 1); if (amdgpu_irq_enabled(adev, source, irq_type)) {
drm_handle_vblank(adev->ddev, crtc);
} }
DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
break; break;
case 1: /* vline */ case 1: /* vline */
if (disp_int & interrupt_status_offsets[crtc].vline) { if (disp_int & interrupt_status_offsets[crtc].vline)
dce_v11_0_crtc_vline_int_ack(adev, crtc); dce_v11_0_crtc_vline_int_ack(adev, crtc);
DRM_DEBUG("IH: D%d vline\n", crtc + 1); else
} DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
DRM_DEBUG("IH: D%d vline\n", crtc + 1);
break; break;
default: default:
DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);

22
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
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@ -3237,19 +3237,25 @@ static int dce_v8_0_crtc_irq(struct amdgpu_device *adev,
switch (entry->src_data) { switch (entry->src_data) {
case 0: /* vblank */ case 0: /* vblank */
if (disp_int & interrupt_status_offsets[crtc].vblank) { if (disp_int & interrupt_status_offsets[crtc].vblank)
WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK); WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);
if (amdgpu_irq_enabled(adev, source, irq_type)) { else
drm_handle_vblank(adev->ddev, crtc); DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
}
DRM_DEBUG("IH: D%d vblank\n", crtc + 1); if (amdgpu_irq_enabled(adev, source, irq_type)) {
drm_handle_vblank(adev->ddev, crtc);
} }
DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
break; break;
case 1: /* vline */ case 1: /* vline */
if (disp_int & interrupt_status_offsets[crtc].vline) { if (disp_int & interrupt_status_offsets[crtc].vline)
WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK); WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);
DRM_DEBUG("IH: D%d vline\n", crtc + 1); else
} DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
DRM_DEBUG("IH: D%d vline\n", crtc + 1);
break; break;
default: default:
DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);

9
drivers/gpu/drm/amd/amdkfd/kfd_process.c
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@ -420,6 +420,12 @@ void kfd_unbind_process_from_device(struct kfd_dev *dev, unsigned int pasid)
pqm_uninit(&p->pqm); pqm_uninit(&p->pqm);
pdd = kfd_get_process_device_data(dev, p); pdd = kfd_get_process_device_data(dev, p);
if (!pdd) {
mutex_unlock(&p->mutex);
return;
}
if (pdd->reset_wavefronts) { if (pdd->reset_wavefronts) {
dbgdev_wave_reset_wavefronts(pdd->dev, p); dbgdev_wave_reset_wavefronts(pdd->dev, p);
pdd->reset_wavefronts = false; pdd->reset_wavefronts = false;
@ -431,8 +437,7 @@ void kfd_unbind_process_from_device(struct kfd_dev *dev, unsigned int pasid)
* We don't call amd_iommu_unbind_pasid() here * We don't call amd_iommu_unbind_pasid() here
* because the IOMMU called us. * because the IOMMU called us.
*/ */
if (pdd) pdd->bound = false;
pdd->bound = false;
mutex_unlock(&p->mutex); mutex_unlock(&p->mutex);
} }

4
drivers/gpu/drm/i915/i915_gem_context.c
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@ -157,9 +157,7 @@ i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
struct drm_i915_gem_object *obj; struct drm_i915_gem_object *obj;
int ret; int ret;
obj = i915_gem_object_create_stolen(dev, size); obj = i915_gem_alloc_object(dev, size);
if (obj == NULL)
obj = i915_gem_alloc_object(dev, size);
if (obj == NULL) if (obj == NULL)
return ERR_PTR(-ENOMEM); return ERR_PTR(-ENOMEM);

23
drivers/gpu/drm/i915/i915_gem_gtt.c
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@ -2546,6 +2546,8 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_i915_gem_object *obj; struct drm_i915_gem_object *obj;
struct i915_address_space *vm; struct i915_address_space *vm;
struct i915_vma *vma;
bool flush;
i915_check_and_clear_faults(dev); i915_check_and_clear_faults(dev);
@ -2555,16 +2557,23 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
dev_priv->gtt.base.total, dev_priv->gtt.base.total,
true); true);
/* Cache flush objects bound into GGTT and rebind them. */
vm = &dev_priv->gtt.base;
list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
struct i915_vma *vma = i915_gem_obj_to_vma(obj, flush = false;
&dev_priv->gtt.base); list_for_each_entry(vma, &obj->vma_list, vma_link) {
if (!vma) if (vma->vm != vm)
continue; continue;
i915_gem_clflush_object(obj, obj->pin_display); WARN_ON(i915_vma_bind(vma, obj->cache_level,
WARN_ON(i915_vma_bind(vma, obj->cache_level, PIN_UPDATE)); PIN_UPDATE));
}
flush = true;
}
if (flush)
i915_gem_clflush_object(obj, obj->pin_display);
}
if (INTEL_INFO(dev)->gen >= 8) { if (INTEL_INFO(dev)->gen >= 8) {
if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))

12
drivers/gpu/drm/i915/i915_gem_tiling.c
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@ -183,8 +183,18 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
if (IS_GEN4(dev)) { if (IS_GEN4(dev)) {
uint32_t ddc2 = I915_READ(DCC2); uint32_t ddc2 = I915_READ(DCC2);
if (!(ddc2 & DCC2_MODIFIED_ENHANCED_DISABLE)) if (!(ddc2 & DCC2_MODIFIED_ENHANCED_DISABLE)) {
/* Since the swizzling may vary within an
* object, we have no idea what the swizzling
* is for any page in particular. Thus we
* cannot migrate tiled pages using the GPU,
* nor can we tell userspace what the exact
* swizzling is for any object.
*/
dev_priv->quirks |= QUIRK_PIN_SWIZZLED_PAGES; dev_priv->quirks |= QUIRK_PIN_SWIZZLED_PAGES;
swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
}
} }
if (dcc == 0xffffffff) { if (dcc == 0xffffffff) {

12
drivers/gpu/drm/i915/intel_display.c
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@ -4854,6 +4854,9 @@ static void intel_crtc_disable_planes(struct drm_crtc *crtc)
struct intel_plane *intel_plane; struct intel_plane *intel_plane;
int pipe = intel_crtc->pipe; int pipe = intel_crtc->pipe;
if (!intel_crtc->active)
return;
intel_crtc_wait_for_pending_flips(crtc); intel_crtc_wait_for_pending_flips(crtc);
intel_pre_disable_primary(crtc); intel_pre_disable_primary(crtc);
@ -7887,7 +7890,7 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
int pipe = pipe_config->cpu_transcoder; int pipe = pipe_config->cpu_transcoder;
enum dpio_channel port = vlv_pipe_to_channel(pipe); enum dpio_channel port = vlv_pipe_to_channel(pipe);
intel_clock_t clock; intel_clock_t clock;
u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
int refclk = 100000; int refclk = 100000;
mutex_lock(&dev_priv->sb_lock); mutex_lock(&dev_priv->sb_lock);
@ -7895,10 +7898,13 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
mutex_unlock(&dev_priv->sb_lock); mutex_unlock(&dev_priv->sb_lock);
clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); clock.m2 = (pll_dw0 & 0xff) << 22;
if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
clock.m2 |= pll_dw2 & 0x3fffff;
clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
@ -13270,7 +13276,7 @@ intel_check_primary_plane(struct drm_plane *plane,
if (ret) if (ret)
return ret; return ret;
if (intel_crtc->active) { if (crtc_state->base.active) {
struct intel_plane_state *old_state = struct intel_plane_state *old_state =
to_intel_plane_state(plane->state); to_intel_plane_state(plane->state);

2
drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
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@ -285,7 +285,7 @@ static int dmm_txn_commit(struct dmm_txn *txn, bool wait)
if (wait) { if (wait) {
if (!wait_for_completion_timeout(&engine->compl, if (!wait_for_completion_timeout(&engine->compl,
msecs_to_jiffies(1))) { msecs_to_jiffies(100))) {
dev_err(dmm->dev, "timed out waiting for done\n"); dev_err(dmm->dev, "timed out waiting for done\n");
ret = -ETIMEDOUT; ret = -ETIMEDOUT;
} }

6
drivers/gpu/drm/omapdrm/omap_drv.h
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@ -177,7 +177,7 @@ struct drm_framebuffer *omap_framebuffer_init(struct drm_device *dev,
struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos); struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos);
struct drm_gem_object *omap_framebuffer_bo(struct drm_framebuffer *fb, int p); struct drm_gem_object *omap_framebuffer_bo(struct drm_framebuffer *fb, int p);
int omap_framebuffer_pin(struct drm_framebuffer *fb); int omap_framebuffer_pin(struct drm_framebuffer *fb);
int omap_framebuffer_unpin(struct drm_framebuffer *fb); void omap_framebuffer_unpin(struct drm_framebuffer *fb);
void omap_framebuffer_update_scanout(struct drm_framebuffer *fb, void omap_framebuffer_update_scanout(struct drm_framebuffer *fb,
struct omap_drm_window *win, struct omap_overlay_info *info); struct omap_drm_window *win, struct omap_overlay_info *info);
struct drm_connector *omap_framebuffer_get_next_connector( struct drm_connector *omap_framebuffer_get_next_connector(
@ -211,7 +211,7 @@ void omap_gem_dma_sync(struct drm_gem_object *obj,
enum dma_data_direction dir); enum dma_data_direction dir);
int omap_gem_get_paddr(struct drm_gem_object *obj, int omap_gem_get_paddr(struct drm_gem_object *obj,
dma_addr_t *paddr, bool remap); dma_addr_t *paddr, bool remap);
int omap_gem_put_paddr(struct drm_gem_object *obj); void omap_gem_put_paddr(struct drm_gem_object *obj);
int omap_gem_get_pages(struct drm_gem_object *obj, struct page ***pages, int omap_gem_get_pages(struct drm_gem_object *obj, struct page ***pages,
bool remap); bool remap);
int omap_gem_put_pages(struct drm_gem_object *obj); int omap_gem_put_pages(struct drm_gem_object *obj);
@ -236,7 +236,7 @@ static inline int align_pitch(int pitch, int width, int bpp)
/* PVR needs alignment to 8 pixels.. right now that is the most /* PVR needs alignment to 8 pixels.. right now that is the most
* restrictive stride requirement.. * restrictive stride requirement..
*/ */
return ALIGN(pitch, 8 * bytespp); return roundup(pitch, 8 * bytespp);
} }
/* map crtc to vblank mask */ /* map crtc to vblank mask */

16
drivers/gpu/drm/omapdrm/omap_fb.c
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@ -287,10 +287,10 @@ fail:
} }
/* unpin, no longer being scanned out: */ /* unpin, no longer being scanned out: */
int omap_framebuffer_unpin(struct drm_framebuffer *fb) void omap_framebuffer_unpin(struct drm_framebuffer *fb)
{ {
struct omap_framebuffer *omap_fb = to_omap_framebuffer(fb); struct omap_framebuffer *omap_fb = to_omap_framebuffer(fb);
int ret, i, n = drm_format_num_planes(fb->pixel_format); int i, n = drm_format_num_planes(fb->pixel_format);
mutex_lock(&omap_fb->lock); mutex_lock(&omap_fb->lock);
@ -298,24 +298,16 @@ int omap_framebuffer_unpin(struct drm_framebuffer *fb)
if (omap_fb->pin_count > 0) { if (omap_fb->pin_count > 0) {
mutex_unlock(&omap_fb->lock); mutex_unlock(&omap_fb->lock);
return 0; return;
} }
for (i = 0; i < n; i++) { for (i = 0; i < n; i++) {
struct plane *plane = &omap_fb->planes[i]; struct plane *plane = &omap_fb->planes[i];
ret = omap_gem_put_paddr(plane->bo); omap_gem_put_paddr(plane->bo);
if (ret)
goto fail;
plane->paddr = 0; plane->paddr = 0;
} }
mutex_unlock(&omap_fb->lock); mutex_unlock(&omap_fb->lock);
return 0;
fail:
mutex_unlock(&omap_fb->lock);
return ret;
} }
struct drm_gem_object *omap_framebuffer_bo(struct drm_framebuffer *fb, int p) struct drm_gem_object *omap_framebuffer_bo(struct drm_framebuffer *fb, int p)

2
drivers/gpu/drm/omapdrm/omap_fbdev.c
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@ -135,7 +135,7 @@ static int omap_fbdev_create(struct drm_fb_helper *helper,
fbdev->ywrap_enabled = priv->has_dmm && ywrap_enabled; fbdev->ywrap_enabled = priv->has_dmm && ywrap_enabled;
if (fbdev->ywrap_enabled) { if (fbdev->ywrap_enabled) {
/* need to align pitch to page size if using DMM scrolling */ /* need to align pitch to page size if using DMM scrolling */
mode_cmd.pitches[0] = ALIGN(mode_cmd.pitches[0], PAGE_SIZE); mode_cmd.pitches[0] = PAGE_ALIGN(mode_cmd.pitches[0]);
} }
/* allocate backing bo */ /* allocate backing bo */

26
drivers/gpu/drm/omapdrm/omap_gem.c
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@ -808,10 +808,10 @@ fail:
/* Release physical address, when DMA is no longer being performed.. this /* Release physical address, when DMA is no longer being performed.. this
* could potentially unpin and unmap buffers from TILER * could potentially unpin and unmap buffers from TILER
*/ */
int omap_gem_put_paddr(struct drm_gem_object *obj) void omap_gem_put_paddr(struct drm_gem_object *obj)
{ {
struct omap_gem_object *omap_obj = to_omap_bo(obj); struct omap_gem_object *omap_obj = to_omap_bo(obj);
int ret = 0; int ret;
mutex_lock(&obj->dev->struct_mutex); mutex_lock(&obj->dev->struct_mutex);
if (omap_obj->paddr_cnt > 0) { if (omap_obj->paddr_cnt > 0) {
@ -821,7 +821,6 @@ int omap_gem_put_paddr(struct drm_gem_object *obj)
if (ret) { if (ret) {
dev_err(obj->dev->dev, dev_err(obj->dev->dev,
"could not unpin pages: %d\n", ret); "could not unpin pages: %d\n", ret);
goto fail;
} }
ret = tiler_release(omap_obj->block); ret = tiler_release(omap_obj->block);
if (ret) { if (ret) {
@ -832,9 +831,8 @@ int omap_gem_put_paddr(struct drm_gem_object *obj)
omap_obj->block = NULL; omap_obj->block = NULL;
} }
} }
fail:
mutex_unlock(&obj->dev->struct_mutex); mutex_unlock(&obj->dev->struct_mutex);
return ret;
} }
/* Get rotated scanout address (only valid if already pinned), at the /* Get rotated scanout address (only valid if already pinned), at the
@ -1378,11 +1376,7 @@ struct drm_gem_object *omap_gem_new(struct drm_device *dev,
omap_obj = kzalloc(sizeof(*omap_obj), GFP_KERNEL); omap_obj = kzalloc(sizeof(*omap_obj), GFP_KERNEL);
if (!omap_obj) if (!omap_obj)
goto fail; return NULL;
spin_lock(&priv->list_lock);
list_add(&omap_obj->mm_list, &priv->obj_list);
spin_unlock(&priv->list_lock);
obj = &omap_obj->base; obj = &omap_obj->base;
@ -1392,11 +1386,19 @@ struct drm_gem_object *omap_gem_new(struct drm_device *dev,
*/ */
omap_obj->vaddr = dma_alloc_writecombine(dev->dev, size, omap_obj->vaddr = dma_alloc_writecombine(dev->dev, size,
&omap_obj->paddr, GFP_KERNEL); &omap_obj->paddr, GFP_KERNEL);
if (omap_obj->vaddr) if (!omap_obj->vaddr) {
flags |= OMAP_BO_DMA; kfree(omap_obj);
return NULL;
}
flags |= OMAP_BO_DMA;
} }
spin_lock(&priv->list_lock);
list_add(&omap_obj->mm_list, &priv->obj_list);
spin_unlock(&priv->list_lock);
omap_obj->flags = flags; omap_obj->flags = flags;
if (flags & OMAP_BO_TILED) { if (flags & OMAP_BO_TILED) {

26
drivers/gpu/drm/omapdrm/omap_plane.c
Unescape View File

@ -17,6 +17,7 @@
* this program. If not, see <http://www.gnu.org/licenses/>. * this program. If not, see <http://www.gnu.org/licenses/>.
*/ */
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h> #include <drm/drm_atomic_helper.h>
#include <drm/drm_plane_helper.h> #include <drm/drm_plane_helper.h>
@ -153,9 +154,34 @@ static void omap_plane_atomic_disable(struct drm_plane *plane,
dispc_ovl_enable(omap_plane->id, false); dispc_ovl_enable(omap_plane->id, false);
} }
static int omap_plane_atomic_check(struct drm_plane *plane,
struct drm_plane_state *state)
{
struct drm_crtc_state *crtc_state;
if (!state->crtc)
return 0;
crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
if (IS_ERR(crtc_state))
return PTR_ERR(crtc_state);
if (state->crtc_x < 0 || state->crtc_y < 0)
return -EINVAL;
if (state->crtc_x + state->crtc_w > crtc_state->adjusted_mode.hdisplay)
return -EINVAL;
if (state->crtc_y + state->crtc_h > crtc_state->adjusted_mode.vdisplay)
return -EINVAL;
return 0;
}
static const struct drm_plane_helper_funcs omap_plane_helper_funcs = { static const struct drm_plane_helper_funcs omap_plane_helper_funcs = {
.prepare_fb = omap_plane_prepare_fb, .prepare_fb = omap_plane_prepare_fb,
.cleanup_fb = omap_plane_cleanup_fb, .cleanup_fb = omap_plane_cleanup_fb,
.atomic_check = omap_plane_atomic_check,
.atomic_update = omap_plane_atomic_update, .atomic_update = omap_plane_atomic_update,
.atomic_disable = omap_plane_atomic_disable, .atomic_disable = omap_plane_atomic_disable,
}; };

336
drivers/gpu/drm/radeon/cik.c
Unescape View File

@ -7964,23 +7964,27 @@ restart_ih:
case 1: /* D1 vblank/vline */ case 1: /* D1 vblank/vline */
switch (src_data) { switch (src_data) {
case 0: /* D1 vblank */ case 0: /* D1 vblank */
if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT) { if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT))
if (rdev->irq.crtc_vblank_int[0]) { DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
drm_handle_vblank(rdev->ddev, 0);
rdev->pm.vblank_sync = true; if (rdev->irq.crtc_vblank_int[0]) {
wake_up(&rdev->irq.vblank_queue); drm_handle_vblank(rdev->ddev, 0);
} rdev->pm.vblank_sync = true;
if (atomic_read(&rdev->irq.pflip[0])) wake_up(&rdev->irq.vblank_queue);
radeon_crtc_handle_vblank(rdev, 0);
rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D1 vblank\n");
} }
if (atomic_read(&rdev->irq.pflip[0]))
radeon_crtc_handle_vblank(rdev, 0);
rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D1 vblank\n");
break; break;
case 1: /* D1 vline */ case 1: /* D1 vline */
if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT) { if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT))
rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VLINE_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
DRM_DEBUG("IH: D1 vline\n");
} rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VLINE_INTERRUPT;
DRM_DEBUG("IH: D1 vline\n");
break; break;
default: default:
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@ -7990,23 +7994,27 @@ restart_ih:
case 2: /* D2 vblank/vline */ case 2: /* D2 vblank/vline */
switch (src_data) { switch (src_data) {
case 0: /* D2 vblank */ case 0: /* D2 vblank */
if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VBLANK_INTERRUPT) { if (!(rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VBLANK_INTERRUPT))
if (rdev->irq.crtc_vblank_int[1]) { DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
drm_handle_vblank(rdev->ddev, 1);
rdev->pm.vblank_sync = true; if (rdev->irq.crtc_vblank_int[1]) {
wake_up(&rdev->irq.vblank_queue); drm_handle_vblank(rdev->ddev, 1);
} rdev->pm.vblank_sync = true;
if (atomic_read(&rdev->irq.pflip[1])) wake_up(&rdev->irq.vblank_queue);
radeon_crtc_handle_vblank(rdev, 1);
rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D2 vblank\n");
} }
if (atomic_read(&rdev->irq.pflip[1]))
radeon_crtc_handle_vblank(rdev, 1);
rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D2 vblank\n");
break; break;
case 1: /* D2 vline */ case 1: /* D2 vline */
if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VLINE_INTERRUPT) { if (!(rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VLINE_INTERRUPT))
rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
DRM_DEBUG("IH: D2 vline\n");
} rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
DRM_DEBUG("IH: D2 vline\n");
break; break;
default: default:
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@ -8016,23 +8024,27 @@ restart_ih:
case 3: /* D3 vblank/vline */ case 3: /* D3 vblank/vline */
switch (src_data) { switch (src_data) {
case 0: /* D3 vblank */ case 0: /* D3 vblank */
if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) { if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT))
if (rdev->irq.crtc_vblank_int[2]) { DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
drm_handle_vblank(rdev->ddev, 2);
rdev->pm.vblank_sync = true; if (rdev->irq.crtc_vblank_int[2]) {
wake_up(&rdev->irq.vblank_queue); drm_handle_vblank(rdev->ddev, 2);
} rdev->pm.vblank_sync = true;
if (atomic_read(&rdev->irq.pflip[2])) wake_up(&rdev->irq.vblank_queue);
radeon_crtc_handle_vblank(rdev, 2);
rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D3 vblank\n");
} }
if (atomic_read(&rdev->irq.pflip[2]))
radeon_crtc_handle_vblank(rdev, 2);
rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D3 vblank\n");
break; break;
case 1: /* D3 vline */ case 1: /* D3 vline */
if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) { if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT))
rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
DRM_DEBUG("IH: D3 vline\n");
} rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
DRM_DEBUG("IH: D3 vline\n");
break; break;
default: default:
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@ -8042,23 +8054,27 @@ restart_ih:
case 4: /* D4 vblank/vline */ case 4: /* D4 vblank/vline */
switch (src_data) { switch (src_data) {
case 0: /* D4 vblank */ case 0: /* D4 vblank */
if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) { if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT))
if (rdev->irq.crtc_vblank_int[3]) { DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
drm_handle_vblank(rdev->ddev, 3);
rdev->pm.vblank_sync = true; if (rdev->irq.crtc_vblank_int[3]) {
wake_up(&rdev->irq.vblank_queue); drm_handle_vblank(rdev->ddev, 3);
} rdev->pm.vblank_sync = true;
if (atomic_read(&rdev->irq.pflip[3])) wake_up(&rdev->irq.vblank_queue);
radeon_crtc_handle_vblank(rdev, 3);
rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D4 vblank\n");
} }
if (atomic_read(&rdev->irq.pflip[3]))
radeon_crtc_handle_vblank(rdev, 3);
rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D4 vblank\n");
break; break;
case 1: /* D4 vline */ case 1: /* D4 vline */
if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) { if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VLINE_INTERRUPT))
rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
DRM_DEBUG("IH: D4 vline\n");
} rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
DRM_DEBUG("IH: D4 vline\n");
break; break;
default: default:
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@ -8068,23 +8084,27 @@ restart_ih:
case 5: /* D5 vblank/vline */ case 5: /* D5 vblank/vline */
switch (src_data) { switch (src_data) {
case 0: /* D5 vblank */ case 0: /* D5 vblank */
if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) { if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT))
if (rdev->irq.crtc_vblank_int[4]) { DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
drm_handle_vblank(rdev->ddev, 4);
rdev->pm.vblank_sync = true; if (rdev->irq.crtc_vblank_int[4]) {
wake_up(&rdev->irq.vblank_queue); drm_handle_vblank(rdev->ddev, 4);
} rdev->pm.vblank_sync = true;
if (atomic_read(&rdev->irq.pflip[4])) wake_up(&rdev->irq.vblank_queue);
radeon_crtc_handle_vblank(rdev, 4);
rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D5 vblank\n");
} }
if (atomic_read(&rdev->irq.pflip[4]))
radeon_crtc_handle_vblank(rdev, 4);
rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D5 vblank\n");
break; break;
case 1: /* D5 vline */ case 1: /* D5 vline */
if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) { if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT))
rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
DRM_DEBUG("IH: D5 vline\n");
} rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
DRM_DEBUG("IH: D5 vline\n");
break; break;
default: default:
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@ -8094,23 +8114,27 @@ restart_ih:
case 6: /* D6 vblank/vline */ case 6: /* D6 vblank/vline */
switch (src_data) { switch (src_data) {
case 0: /* D6 vblank */ case 0: /* D6 vblank */
if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) { if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT))
if (rdev->irq.crtc_vblank_int[5]) { DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
drm_handle_vblank(rdev->ddev, 5);
rdev->pm.vblank_sync = true; if (rdev->irq.crtc_vblank_int[5]) {
wake_up(&rdev->irq.vblank_queue); drm_handle_vblank(rdev->ddev, 5);
} rdev->pm.vblank_sync = true;
if (atomic_read(&rdev->irq.pflip[5])) wake_up(&rdev->irq.vblank_queue);
radeon_crtc_handle_vblank(rdev, 5);
rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D6 vblank\n");
} }
if (atomic_read(&rdev->irq.pflip[5]))
radeon_crtc_handle_vblank(rdev, 5);
rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D6 vblank\n");
break; break;
case 1: /* D6 vline */ case 1: /* D6 vline */
if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) { if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VLINE_INTERRUPT))
rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
DRM_DEBUG("IH: D6 vline\n");
} rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
DRM_DEBUG("IH: D6 vline\n");
break; break;
default: default:
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@ -8130,88 +8154,112 @@ restart_ih:
case 42: /* HPD hotplug */ case 42: /* HPD hotplug */
switch (src_data) { switch (src_data) {
case 0: case 0:
if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT) { if (!(rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT))
rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_hotplug = true;
DRM_DEBUG("IH: HPD1\n"); rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_INTERRUPT;
} queue_hotplug = true;
DRM_DEBUG("IH: HPD1\n");
break; break;
case 1: case 1:
if (rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_INTERRUPT) { if (!(rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_INTERRUPT))
rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_hotplug = true;
DRM_DEBUG("IH: HPD2\n"); rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_INTERRUPT;
} queue_hotplug = true;
DRM_DEBUG("IH: HPD2\n");
break; break;
case 2: case 2:
if (rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_INTERRUPT) { if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_INTERRUPT))
rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_hotplug = true;
DRM_DEBUG("IH: HPD3\n"); rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
} queue_hotplug = true;
DRM_DEBUG("IH: HPD3\n");
break; break;
case 3: case 3:
if (rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_INTERRUPT) { if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_INTERRUPT))
rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_hotplug = true;
DRM_DEBUG("IH: HPD4\n"); rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
} queue_hotplug = true;
DRM_DEBUG("IH: HPD4\n");
break; break;
case 4: case 4:
if (rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_INTERRUPT) { if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_INTERRUPT))
rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_hotplug = true;
DRM_DEBUG("IH: HPD5\n"); rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
} queue_hotplug = true;
DRM_DEBUG("IH: HPD5\n");
break; break;
case 5: case 5:
if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT) { if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT))
rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_hotplug = true;
DRM_DEBUG("IH: HPD6\n"); rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
} queue_hotplug = true;
DRM_DEBUG("IH: HPD6\n");
break; break;
case 6: case 6:
if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_RX_INTERRUPT) { if (!(rdev->irq.stat_regs.cik.disp_int & DC_HPD1_RX_INTERRUPT))
rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_RX_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_dp = true;
DRM_DEBUG("IH: HPD_RX 1\n"); rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_RX_INTERRUPT;
} queue_dp = true;
DRM_DEBUG("IH: HPD_RX 1\n");
break; break;
case 7: case 7:
if (rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_RX_INTERRUPT) { if (!(rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_RX_INTERRUPT))
rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_dp = true;
DRM_DEBUG("IH: HPD_RX 2\n"); rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT;
} queue_dp = true;
DRM_DEBUG("IH: HPD_RX 2\n");
break; break;
case 8: case 8:
if (rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_RX_INTERRUPT) { if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_RX_INTERRUPT))
rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_dp = true;
DRM_DEBUG("IH: HPD_RX 3\n"); rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT;
} queue_dp = true;
DRM_DEBUG("IH: HPD_RX 3\n");
break; break;
case 9: case 9:
if (rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_RX_INTERRUPT) { if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_RX_INTERRUPT))
rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_dp = true;
DRM_DEBUG("IH: HPD_RX 4\n"); rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT;
} queue_dp = true;
DRM_DEBUG("IH: HPD_RX 4\n");
break; break;
case 10: case 10:
if (rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_RX_INTERRUPT) { if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_RX_INTERRUPT))
rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_dp = true;
DRM_DEBUG("IH: HPD_RX 5\n"); rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT;
} queue_dp = true;
DRM_DEBUG("IH: HPD_RX 5\n");
break; break;
case 11: case 11:
if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) { if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_RX_INTERRUPT))
rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_dp = true;
DRM_DEBUG("IH: HPD_RX 6\n"); rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT;
} queue_dp = true;
DRM_DEBUG("IH: HPD_RX 6\n");
break; break;
default: default:
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);

392
drivers/gpu/drm/radeon/evergreen.c
Unescape View File

@ -4924,7 +4924,7 @@ restart_ih:
return IRQ_NONE; return IRQ_NONE;
rptr = rdev->ih.rptr; rptr = rdev->ih.rptr;
DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); DRM_DEBUG("evergreen_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
/* Order reading of wptr vs. reading of IH ring data */ /* Order reading of wptr vs. reading of IH ring data */
rmb(); rmb();
@ -4942,23 +4942,27 @@ restart_ih:
case 1: /* D1 vblank/vline */ case 1: /* D1 vblank/vline */
switch (src_data) { switch (src_data) {
case 0: /* D1 vblank */ case 0: /* D1 vblank */
if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT))
if (rdev->irq.crtc_vblank_int[0]) { DRM_DEBUG("IH: D1 vblank - IH event w/o asserted irq bit?\n");
drm_handle_vblank(rdev->ddev, 0);
rdev->pm.vblank_sync = true; if (rdev->irq.crtc_vblank_int[0]) {
wake_up(&rdev->irq.vblank_queue); drm_handle_vblank(rdev->ddev, 0);
} rdev->pm.vblank_sync = true;
if (atomic_read(&rdev->irq.pflip[0])) wake_up(&rdev->irq.vblank_queue);
radeon_crtc_handle_vblank(rdev, 0);
rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D1 vblank\n");
} }
if (atomic_read(&rdev->irq.pflip[0]))
radeon_crtc_handle_vblank(rdev, 0);
rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D1 vblank\n");
break; break;
case 1: /* D1 vline */ case 1: /* D1 vline */
if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT; DRM_DEBUG("IH: D1 vline - IH event w/o asserted irq bit?\n");
DRM_DEBUG("IH: D1 vline\n");
} rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
DRM_DEBUG("IH: D1 vline\n");
break; break;
default: default:
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@ -4968,23 +4972,27 @@ restart_ih:
case 2: /* D2 vblank/vline */ case 2: /* D2 vblank/vline */
switch (src_data) { switch (src_data) {
case 0: /* D2 vblank */ case 0: /* D2 vblank */
if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT))
if (rdev->irq.crtc_vblank_int[1]) { DRM_DEBUG("IH: D2 vblank - IH event w/o asserted irq bit?\n");
drm_handle_vblank(rdev->ddev, 1);
rdev->pm.vblank_sync = true; if (rdev->irq.crtc_vblank_int[1]) {
wake_up(&rdev->irq.vblank_queue); drm_handle_vblank(rdev->ddev, 1);
} rdev->pm.vblank_sync = true;
if (atomic_read(&rdev->irq.pflip[1])) wake_up(&rdev->irq.vblank_queue);
radeon_crtc_handle_vblank(rdev, 1);
rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D2 vblank\n");
} }
if (atomic_read(&rdev->irq.pflip[1]))
radeon_crtc_handle_vblank(rdev, 1);
rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D2 vblank\n");
break; break;
case 1: /* D2 vline */ case 1: /* D2 vline */
if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; DRM_DEBUG("IH: D2 vline - IH event w/o asserted irq bit?\n");
DRM_DEBUG("IH: D2 vline\n");
} rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
DRM_DEBUG("IH: D2 vline\n");
break; break;
default: default:
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@ -4994,23 +5002,27 @@ restart_ih:
case 3: /* D3 vblank/vline */ case 3: /* D3 vblank/vline */
switch (src_data) { switch (src_data) {
case 0: /* D3 vblank */ case 0: /* D3 vblank */
if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT))
if (rdev->irq.crtc_vblank_int[2]) { DRM_DEBUG("IH: D3 vblank - IH event w/o asserted irq bit?\n");
drm_handle_vblank(rdev->ddev, 2);
rdev->pm.vblank_sync = true; if (rdev->irq.crtc_vblank_int[2]) {
wake_up(&rdev->irq.vblank_queue); drm_handle_vblank(rdev->ddev, 2);
} rdev->pm.vblank_sync = true;
if (atomic_read(&rdev->irq.pflip[2])) wake_up(&rdev->irq.vblank_queue);
radeon_crtc_handle_vblank(rdev, 2);
rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D3 vblank\n");
} }
if (atomic_read(&rdev->irq.pflip[2]))
radeon_crtc_handle_vblank(rdev, 2);
rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D3 vblank\n");
break; break;
case 1: /* D3 vline */ case 1: /* D3 vline */
if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; DRM_DEBUG("IH: D3 vline - IH event w/o asserted irq bit?\n");
DRM_DEBUG("IH: D3 vline\n");
} rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
DRM_DEBUG("IH: D3 vline\n");
break; break;
default: default:
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@ -5020,23 +5032,27 @@ restart_ih:
case 4: /* D4 vblank/vline */ case 4: /* D4 vblank/vline */
switch (src_data) { switch (src_data) {
case 0: /* D4 vblank */ case 0: /* D4 vblank */
if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT))
if (rdev->irq.crtc_vblank_int[3]) { DRM_DEBUG("IH: D4 vblank - IH event w/o asserted irq bit?\n");
drm_handle_vblank(rdev->ddev, 3);
rdev->pm.vblank_sync = true; if (rdev->irq.crtc_vblank_int[3]) {
wake_up(&rdev->irq.vblank_queue); drm_handle_vblank(rdev->ddev, 3);
} rdev->pm.vblank_sync = true;
if (atomic_read(&rdev->irq.pflip[3])) wake_up(&rdev->irq.vblank_queue);
radeon_crtc_handle_vblank(rdev, 3);
rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D4 vblank\n");
} }
if (atomic_read(&rdev->irq.pflip[3]))
radeon_crtc_handle_vblank(rdev, 3);
rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D4 vblank\n");
break; break;
case 1: /* D4 vline */ case 1: /* D4 vline */
if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; DRM_DEBUG("IH: D4 vline - IH event w/o asserted irq bit?\n");
DRM_DEBUG("IH: D4 vline\n");
} rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
DRM_DEBUG("IH: D4 vline\n");
break; break;
default: default:
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@ -5046,23 +5062,27 @@ restart_ih:
case 5: /* D5 vblank/vline */ case 5: /* D5 vblank/vline */
switch (src_data) { switch (src_data) {
case 0: /* D5 vblank */ case 0: /* D5 vblank */
if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT))
if (rdev->irq.crtc_vblank_int[4]) { DRM_DEBUG("IH: D5 vblank - IH event w/o asserted irq bit?\n");
drm_handle_vblank(rdev->ddev, 4);
rdev->pm.vblank_sync = true; if (rdev->irq.crtc_vblank_int[4]) {
wake_up(&rdev->irq.vblank_queue); drm_handle_vblank(rdev->ddev, 4);
} rdev->pm.vblank_sync = true;
if (atomic_read(&rdev->irq.pflip[4])) wake_up(&rdev->irq.vblank_queue);
radeon_crtc_handle_vblank(rdev, 4);
rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D5 vblank\n");
} }
if (atomic_read(&rdev->irq.pflip[4]))
radeon_crtc_handle_vblank(rdev, 4);
rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D5 vblank\n");
break; break;
case 1: /* D5 vline */ case 1: /* D5 vline */
if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; DRM_DEBUG("IH: D5 vline - IH event w/o asserted irq bit?\n");
DRM_DEBUG("IH: D5 vline\n");
} rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
DRM_DEBUG("IH: D5 vline\n");
break; break;
default: default:
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@ -5072,23 +5092,27 @@ restart_ih:
case 6: /* D6 vblank/vline */ case 6: /* D6 vblank/vline */
switch (src_data) { switch (src_data) {
case 0: /* D6 vblank */ case 0: /* D6 vblank */
if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT))
if (rdev->irq.crtc_vblank_int[5]) { DRM_DEBUG("IH: D6 vblank - IH event w/o asserted irq bit?\n");
drm_handle_vblank(rdev->ddev, 5);
rdev->pm.vblank_sync = true; if (rdev->irq.crtc_vblank_int[5]) {
wake_up(&rdev->irq.vblank_queue); drm_handle_vblank(rdev->ddev, 5);
} rdev->pm.vblank_sync = true;
if (atomic_read(&rdev->irq.pflip[5])) wake_up(&rdev->irq.vblank_queue);
radeon_crtc_handle_vblank(rdev, 5);
rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D6 vblank\n");
} }
if (atomic_read(&rdev->irq.pflip[5]))
radeon_crtc_handle_vblank(rdev, 5);
rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D6 vblank\n");
break; break;
case 1: /* D6 vline */ case 1: /* D6 vline */
if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; DRM_DEBUG("IH: D6 vline - IH event w/o asserted irq bit?\n");
DRM_DEBUG("IH: D6 vline\n");
} rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
DRM_DEBUG("IH: D6 vline\n");
break; break;
default: default:
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@ -5108,88 +5132,100 @@ restart_ih:
case 42: /* HPD hotplug */ case 42: /* HPD hotplug */
switch (src_data) { switch (src_data) {
case 0: case 0:
if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_hotplug = true;
DRM_DEBUG("IH: HPD1\n"); rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
} queue_hotplug = true;
DRM_DEBUG("IH: HPD1\n");
break; break;
case 1: case 1:
if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_hotplug = true;
DRM_DEBUG("IH: HPD2\n"); rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
} queue_hotplug = true;
DRM_DEBUG("IH: HPD2\n");
break; break;
case 2: case 2:
if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_hotplug = true;
DRM_DEBUG("IH: HPD3\n"); rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
} queue_hotplug = true;
DRM_DEBUG("IH: HPD3\n");
break; break;
case 3: case 3:
if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_hotplug = true;
DRM_DEBUG("IH: HPD4\n"); rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
} queue_hotplug = true;
DRM_DEBUG("IH: HPD4\n");
break; break;
case 4: case 4:
if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_hotplug = true;
DRM_DEBUG("IH: HPD5\n"); rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
} queue_hotplug = true;
DRM_DEBUG("IH: HPD5\n");
break; break;
case 5: case 5:
if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_hotplug = true;
DRM_DEBUG("IH: HPD6\n"); rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
} queue_hotplug = true;
DRM_DEBUG("IH: HPD6\n");
break; break;
case 6: case 6:
if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_RX_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_dp = true;
DRM_DEBUG("IH: HPD_RX 1\n"); rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_RX_INTERRUPT;
} queue_dp = true;
DRM_DEBUG("IH: HPD_RX 1\n");
break; break;
case 7: case 7:
if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_dp = true;
DRM_DEBUG("IH: HPD_RX 2\n"); rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT;
} queue_dp = true;
DRM_DEBUG("IH: HPD_RX 2\n");
break; break;
case 8: case 8:
if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_dp = true;
DRM_DEBUG("IH: HPD_RX 3\n"); rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT;
} queue_dp = true;
DRM_DEBUG("IH: HPD_RX 3\n");
break; break;
case 9: case 9:
if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_dp = true;
DRM_DEBUG("IH: HPD_RX 4\n"); rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT;
} queue_dp = true;
DRM_DEBUG("IH: HPD_RX 4\n");
break; break;
case 10: case 10:
if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_dp = true;
DRM_DEBUG("IH: HPD_RX 5\n"); rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT;
} queue_dp = true;
DRM_DEBUG("IH: HPD_RX 5\n");
break; break;
case 11: case 11:
if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_dp = true;
DRM_DEBUG("IH: HPD_RX 6\n"); rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT;
} queue_dp = true;
DRM_DEBUG("IH: HPD_RX 6\n");
break; break;
default: default:
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@ -5199,46 +5235,52 @@ restart_ih:
case 44: /* hdmi */ case 44: /* hdmi */
switch (src_data) { switch (src_data) {
case 0: case 0:
if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) { if (!(rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG))
rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_hdmi = true;
DRM_DEBUG("IH: HDMI0\n"); rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG;
} queue_hdmi = true;
DRM_DEBUG("IH: HDMI0\n");
break; break;
case 1: case 1:
if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) { if (!(rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG))
rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_hdmi = true;
DRM_DEBUG("IH: HDMI1\n"); rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG;
} queue_hdmi = true;
DRM_DEBUG("IH: HDMI1\n");
break; break;
case 2: case 2:
if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) { if (!(rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG))
rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_hdmi = true;
DRM_DEBUG("IH: HDMI2\n"); rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG;
} queue_hdmi = true;
DRM_DEBUG("IH: HDMI2\n");
break; break;
case 3: case 3:
if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) { if (!(rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG))
rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_hdmi = true;
DRM_DEBUG("IH: HDMI3\n"); rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG;
} queue_hdmi = true;
DRM_DEBUG("IH: HDMI3\n");
break; break;
case 4: case 4:
if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) { if (!(rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG))
rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_hdmi = true;
DRM_DEBUG("IH: HDMI4\n"); rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG;
} queue_hdmi = true;
DRM_DEBUG("IH: HDMI4\n");
break; break;
case 5: case 5:
if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) { if (!(rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG))
rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_hdmi = true;
DRM_DEBUG("IH: HDMI5\n"); rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG;
} queue_hdmi = true;
DRM_DEBUG("IH: HDMI5\n");
break; break;
default: default:
DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);

25
drivers/gpu/drm/radeon/ni.c
Unescape View File

@ -2162,18 +2162,20 @@ static int cayman_startup(struct radeon_device *rdev)
DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
} }
ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; if (rdev->family == CHIP_ARUBA) {
if (ring->ring_size) ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); if (ring->ring_size)
r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0);
ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
if (ring->ring_size) if (ring->ring_size)
r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0);
if (!r) if (!r)
r = vce_v1_0_init(rdev); r = vce_v1_0_init(rdev);
else if (r != -ENOENT) if (r)
DRM_ERROR("radeon: failed initializing VCE (%d).\n", r); DRM_ERROR("radeon: failed initializing VCE (%d).\n", r);
}
r = radeon_ib_pool_init(rdev); r = radeon_ib_pool_init(rdev);
if (r) { if (r) {
@ -2396,7 +2398,8 @@ void cayman_fini(struct radeon_device *rdev)
radeon_irq_kms_fini(rdev); radeon_irq_kms_fini(rdev);
uvd_v1_0_fini(rdev); uvd_v1_0_fini(rdev);
radeon_uvd_fini(rdev); radeon_uvd_fini(rdev);
radeon_vce_fini(rdev); if (rdev->family == CHIP_ARUBA)
radeon_vce_fini(rdev);
cayman_pcie_gart_fini(rdev); cayman_pcie_gart_fini(rdev);
r600_vram_scratch_fini(rdev); r600_vram_scratch_fini(rdev);
radeon_gem_fini(rdev); radeon_gem_fini(rdev);

155
drivers/gpu/drm/radeon/r600.c
Unescape View File

@ -4086,23 +4086,27 @@ restart_ih:
case 1: /* D1 vblank/vline */ case 1: /* D1 vblank/vline */
switch (src_data) { switch (src_data) {
case 0: /* D1 vblank */ case 0: /* D1 vblank */
if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) { if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT))
if (rdev->irq.crtc_vblank_int[0]) { DRM_DEBUG("IH: D1 vblank - IH event w/o asserted irq bit?\n");
drm_handle_vblank(rdev->ddev, 0);
rdev->pm.vblank_sync = true; if (rdev->irq.crtc_vblank_int[0]) {
wake_up(&rdev->irq.vblank_queue); drm_handle_vblank(rdev->ddev, 0);
} rdev->pm.vblank_sync = true;
if (atomic_read(&rdev->irq.pflip[0])) wake_up(&rdev->irq.vblank_queue);
radeon_crtc_handle_vblank(rdev, 0);
rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D1 vblank\n");
} }
if (atomic_read(&rdev->irq.pflip[0]))
radeon_crtc_handle_vblank(rdev, 0);
rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D1 vblank\n");
break; break;
case 1: /* D1 vline */ case 1: /* D1 vline */
if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) { if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT))
rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; DRM_DEBUG("IH: D1 vline - IH event w/o asserted irq bit?\n");
DRM_DEBUG("IH: D1 vline\n");
} rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
DRM_DEBUG("IH: D1 vline\n");
break; break;
default: default:
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@ -4112,23 +4116,27 @@ restart_ih:
case 5: /* D2 vblank/vline */ case 5: /* D2 vblank/vline */
switch (src_data) { switch (src_data) {
case 0: /* D2 vblank */ case 0: /* D2 vblank */
if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) { if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT))
if (rdev->irq.crtc_vblank_int[1]) { DRM_DEBUG("IH: D2 vblank - IH event w/o asserted irq bit?\n");
drm_handle_vblank(rdev->ddev, 1);
rdev->pm.vblank_sync = true; if (rdev->irq.crtc_vblank_int[1]) {
wake_up(&rdev->irq.vblank_queue); drm_handle_vblank(rdev->ddev, 1);
} rdev->pm.vblank_sync = true;
if (atomic_read(&rdev->irq.pflip[1])) wake_up(&rdev->irq.vblank_queue);
radeon_crtc_handle_vblank(rdev, 1);
rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D2 vblank\n");
} }
if (atomic_read(&rdev->irq.pflip[1]))
radeon_crtc_handle_vblank(rdev, 1);
rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D2 vblank\n");
break; break;
case 1: /* D1 vline */ case 1: /* D1 vline */
if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) { if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT))
rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; DRM_DEBUG("IH: D2 vline - IH event w/o asserted irq bit?\n");
DRM_DEBUG("IH: D2 vline\n");
} rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
DRM_DEBUG("IH: D2 vline\n");
break; break;
default: default:
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@ -4148,46 +4156,53 @@ restart_ih:
case 19: /* HPD/DAC hotplug */ case 19: /* HPD/DAC hotplug */
switch (src_data) { switch (src_data) {
case 0: case 0:
if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT))
rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; DRM_DEBUG("IH: HPD1 - IH event w/o asserted irq bit?\n");
queue_hotplug = true;
DRM_DEBUG("IH: HPD1\n"); rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
} queue_hotplug = true;
DRM_DEBUG("IH: HPD1\n");
break; break;
case 1: case 1:
if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT))
rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; DRM_DEBUG("IH: HPD2 - IH event w/o asserted irq bit?\n");
queue_hotplug = true;
DRM_DEBUG("IH: HPD2\n"); rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
} queue_hotplug = true;
DRM_DEBUG("IH: HPD2\n");
break; break;
case 4: case 4:
if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT))
rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; DRM_DEBUG("IH: HPD3 - IH event w/o asserted irq bit?\n");
queue_hotplug = true;
DRM_DEBUG("IH: HPD3\n"); rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
} queue_hotplug = true;
DRM_DEBUG("IH: HPD3\n");
break; break;
case 5: case 5:
if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT))
rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; DRM_DEBUG("IH: HPD4 - IH event w/o asserted irq bit?\n");
queue_hotplug = true;
DRM_DEBUG("IH: HPD4\n"); rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
} queue_hotplug = true;
DRM_DEBUG("IH: HPD4\n");
break; break;
case 10: case 10:
if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT))
rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; DRM_DEBUG("IH: HPD5 - IH event w/o asserted irq bit?\n");
queue_hotplug = true;
DRM_DEBUG("IH: HPD5\n"); rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
} queue_hotplug = true;
DRM_DEBUG("IH: HPD5\n");
break; break;
case 12: case 12:
if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT))
rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; DRM_DEBUG("IH: HPD6 - IH event w/o asserted irq bit?\n");
queue_hotplug = true;
DRM_DEBUG("IH: HPD6\n"); rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
} queue_hotplug = true;
DRM_DEBUG("IH: HPD6\n");
break; break;
default: default:
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@ -4197,18 +4212,22 @@ restart_ih:
case 21: /* hdmi */ case 21: /* hdmi */
switch (src_data) { switch (src_data) {
case 4: case 4:
if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { if (!(rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG))
rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; DRM_DEBUG("IH: HDMI0 - IH event w/o asserted irq bit?\n");
queue_hdmi = true;
DRM_DEBUG("IH: HDMI0\n"); rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
} queue_hdmi = true;
DRM_DEBUG("IH: HDMI0\n");
break; break;
case 5: case 5:
if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { if (!(rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG))
rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; DRM_DEBUG("IH: HDMI1 - IH event w/o asserted irq bit?\n");
queue_hdmi = true;
DRM_DEBUG("IH: HDMI1\n"); rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
} queue_hdmi = true;
DRM_DEBUG("IH: HDMI1\n");
break; break;
default: default:
DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);

2
drivers/gpu/drm/radeon/r600_cp.c
Unescape View File

@ -2483,7 +2483,7 @@ int r600_cp_dispatch_texture(struct drm_device *dev,
struct drm_buf *buf; struct drm_buf *buf;
u32 *buffer; u32 *buffer;
const u8 __user *data; const u8 __user *data;
int size, pass_size; unsigned int size, pass_size;
u64 src_offset, dst_offset; u64 src_offset, dst_offset;
if (!radeon_check_offset(dev_priv, tex->offset)) { if (!radeon_check_offset(dev_priv, tex->offset)) {

109
drivers/gpu/drm/radeon/radeon_cursor.c
Unescape View File

@ -91,15 +91,34 @@ static void radeon_show_cursor(struct drm_crtc *crtc)
struct radeon_device *rdev = crtc->dev->dev_private; struct radeon_device *rdev = crtc->dev->dev_private;
if (ASIC_IS_DCE4(rdev)) { if (ASIC_IS_DCE4(rdev)) {
WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
upper_32_bits(radeon_crtc->cursor_addr));
WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
lower_32_bits(radeon_crtc->cursor_addr));
WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN | WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN |
EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) | EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2)); EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
} else if (ASIC_IS_AVIVO(rdev)) { } else if (ASIC_IS_AVIVO(rdev)) {
if (rdev->family >= CHIP_RV770) {
if (radeon_crtc->crtc_id)
WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH,
upper_32_bits(radeon_crtc->cursor_addr));
else
WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH,
upper_32_bits(radeon_crtc->cursor_addr));
}
WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
lower_32_bits(radeon_crtc->cursor_addr));
WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |
(AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
} else { } else {
/* offset is from DISP(2)_BASE_ADDRESS */
WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset,
radeon_crtc->cursor_addr - radeon_crtc->legacy_display_base_addr);
switch (radeon_crtc->crtc_id) { switch (radeon_crtc->crtc_id) {
case 0: case 0:
WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
@ -205,8 +224,9 @@ static int radeon_cursor_move_locked(struct drm_crtc *crtc, int x, int y)
| (x << 16) | (x << 16)
| y)); | y));
/* offset is from DISP(2)_BASE_ADDRESS */ /* offset is from DISP(2)_BASE_ADDRESS */
WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset + WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset,
(yorigin * 256))); radeon_crtc->cursor_addr - radeon_crtc->legacy_display_base_addr +
yorigin * 256);
} }
radeon_crtc->cursor_x = x; radeon_crtc->cursor_x = x;
@ -227,53 +247,6 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
return ret; return ret;
} }
static int radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj)
{
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
struct radeon_device *rdev = crtc->dev->dev_private;
struct radeon_bo *robj = gem_to_radeon_bo(obj);
uint64_t gpu_addr;
int ret;
ret = radeon_bo_reserve(robj, false);
if (unlikely(ret != 0))
goto fail;
/* Only 27 bit offset for legacy cursor */
ret = radeon_bo_pin_restricted(robj, RADEON_GEM_DOMAIN_VRAM,
ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
&gpu_addr);
radeon_bo_unreserve(robj);
if (ret)
goto fail;
if (ASIC_IS_DCE4(rdev)) {
WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
upper_32_bits(gpu_addr));
WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
gpu_addr & 0xffffffff);
} else if (ASIC_IS_AVIVO(rdev)) {
if (rdev->family >= CHIP_RV770) {
if (radeon_crtc->crtc_id)
WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr));
else
WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr));
}
WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
gpu_addr & 0xffffffff);
} else {
radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr;
/* offset is from DISP(2)_BASE_ADDRESS */
WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset);
}
return 0;
fail:
drm_gem_object_unreference_unlocked(obj);
return ret;
}
int radeon_crtc_cursor_set2(struct drm_crtc *crtc, int radeon_crtc_cursor_set2(struct drm_crtc *crtc,
struct drm_file *file_priv, struct drm_file *file_priv,
uint32_t handle, uint32_t handle,
@ -283,7 +256,9 @@ int radeon_crtc_cursor_set2(struct drm_crtc *crtc,
int32_t hot_y) int32_t hot_y)
{ {
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
struct radeon_device *rdev = crtc->dev->dev_private;
struct drm_gem_object *obj; struct drm_gem_object *obj;
struct radeon_bo *robj;
int ret; int ret;
if (!handle) { if (!handle) {
@ -305,6 +280,23 @@ int radeon_crtc_cursor_set2(struct drm_crtc *crtc,
return -ENOENT; return -ENOENT;
} }
robj = gem_to_radeon_bo(obj);
ret = radeon_bo_reserve(robj, false);
if (ret != 0) {
drm_gem_object_unreference_unlocked(obj);
return ret;
}
/* Only 27 bit offset for legacy cursor */
ret = radeon_bo_pin_restricted(robj, RADEON_GEM_DOMAIN_VRAM,
ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
&radeon_crtc->cursor_addr);
radeon_bo_unreserve(robj);
if (ret) {
DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
drm_gem_object_unreference_unlocked(obj);
return ret;
}
radeon_crtc->cursor_width = width; radeon_crtc->cursor_width = width;
radeon_crtc->cursor_height = height; radeon_crtc->cursor_height = height;
@ -323,13 +315,7 @@ int radeon_crtc_cursor_set2(struct drm_crtc *crtc,
radeon_crtc->cursor_hot_y = hot_y; radeon_crtc->cursor_hot_y = hot_y;
} }
ret = radeon_set_cursor(crtc, obj); radeon_show_cursor(crtc);
if (ret)
DRM_ERROR("radeon_set_cursor returned %d, not changing cursor\n",
ret);
else
radeon_show_cursor(crtc);
radeon_lock_cursor(crtc, false); radeon_lock_cursor(crtc, false);
@ -341,8 +327,7 @@ unpin:
radeon_bo_unpin(robj); radeon_bo_unpin(robj);
radeon_bo_unreserve(robj); radeon_bo_unreserve(robj);
} }
if (radeon_crtc->cursor_bo != obj) drm_gem_object_unreference_unlocked(radeon_crtc->cursor_bo);
drm_gem_object_unreference_unlocked(radeon_crtc->cursor_bo);
} }
radeon_crtc->cursor_bo = obj; radeon_crtc->cursor_bo = obj;
@ -360,7 +345,6 @@ unpin:
void radeon_cursor_reset(struct drm_crtc *crtc) void radeon_cursor_reset(struct drm_crtc *crtc)
{ {
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
int ret;
if (radeon_crtc->cursor_bo) { if (radeon_crtc->cursor_bo) {
radeon_lock_cursor(crtc, true); radeon_lock_cursor(crtc, true);
@ -368,12 +352,7 @@ void radeon_cursor_reset(struct drm_crtc *crtc)
radeon_cursor_move_locked(crtc, radeon_crtc->cursor_x, radeon_cursor_move_locked(crtc, radeon_crtc->cursor_x,
radeon_crtc->cursor_y); radeon_crtc->cursor_y);
ret = radeon_set_cursor(crtc, radeon_crtc->cursor_bo); radeon_show_cursor(crtc);
if (ret)
DRM_ERROR("radeon_set_cursor returned %d, not showing "
"cursor\n", ret);
else
radeon_show_cursor(crtc);
radeon_lock_cursor(crtc, false); radeon_lock_cursor(crtc, false);
} }

66
drivers/gpu/drm/radeon/radeon_device.c
Unescape View File

@ -1079,6 +1079,22 @@ static bool radeon_check_pot_argument(int arg)
return (arg & (arg - 1)) == 0; return (arg & (arg - 1)) == 0;
} }
/**
* Determine a sensible default GART size according to ASIC family.
*
* @family ASIC family name
*/
static int radeon_gart_size_auto(enum radeon_family family)
{
/* default to a larger gart size on newer asics */
if (family >= CHIP_TAHITI)
return 2048;
else if (family >= CHIP_RV770)
return 1024;
else
return 512;
}
/** /**
* radeon_check_arguments - validate module params * radeon_check_arguments - validate module params
* *
@ -1097,27 +1113,17 @@ static void radeon_check_arguments(struct radeon_device *rdev)
} }
if (radeon_gart_size == -1) { if (radeon_gart_size == -1) {
/* default to a larger gart size on newer asics */ radeon_gart_size = radeon_gart_size_auto(rdev->family);
if (rdev->family >= CHIP_RV770)
radeon_gart_size = 1024;
else
radeon_gart_size = 512;
} }
/* gtt size must be power of two and greater or equal to 32M */ /* gtt size must be power of two and greater or equal to 32M */
if (radeon_gart_size < 32) { if (radeon_gart_size < 32) {
dev_warn(rdev->dev, "gart size (%d) too small\n", dev_warn(rdev->dev, "gart size (%d) too small\n",
radeon_gart_size); radeon_gart_size);
if (rdev->family >= CHIP_RV770) radeon_gart_size = radeon_gart_size_auto(rdev->family);
radeon_gart_size = 1024;
else
radeon_gart_size = 512;
} else if (!radeon_check_pot_argument(radeon_gart_size)) { } else if (!radeon_check_pot_argument(radeon_gart_size)) {
dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
radeon_gart_size); radeon_gart_size);
if (rdev->family >= CHIP_RV770) radeon_gart_size = radeon_gart_size_auto(rdev->family);
radeon_gart_size = 1024;
else
radeon_gart_size = 512;
} }
rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20; rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
@ -1572,11 +1578,21 @@ int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
} }
/* unpin the front buffers */ /* unpin the front buffers and cursors */
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->primary->fb); struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->primary->fb);
struct radeon_bo *robj; struct radeon_bo *robj;
if (radeon_crtc->cursor_bo) {
struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
r = radeon_bo_reserve(robj, false);
if (r == 0) {
radeon_bo_unpin(robj);
radeon_bo_unreserve(robj);
}
}
if (rfb == NULL || rfb->obj == NULL) { if (rfb == NULL || rfb->obj == NULL) {
continue; continue;
} }
@ -1639,6 +1655,7 @@ int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
{ {
struct drm_connector *connector; struct drm_connector *connector;
struct radeon_device *rdev = dev->dev_private; struct radeon_device *rdev = dev->dev_private;
struct drm_crtc *crtc;
int r; int r;
if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
@ -1678,6 +1695,27 @@ int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
radeon_restore_bios_scratch_regs(rdev); radeon_restore_bios_scratch_regs(rdev);
/* pin cursors */
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
if (radeon_crtc->cursor_bo) {
struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
r = radeon_bo_reserve(robj, false);
if (r == 0) {
/* Only 27 bit offset for legacy cursor */
r = radeon_bo_pin_restricted(robj,
RADEON_GEM_DOMAIN_VRAM,
ASIC_IS_AVIVO(rdev) ?
0 : 1 << 27,
&radeon_crtc->cursor_addr);
if (r != 0)
DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
radeon_bo_unreserve(robj);
}
}
}
/* init dig PHYs, disp eng pll */ /* init dig PHYs, disp eng pll */
if (rdev->is_atom_bios) { if (rdev->is_atom_bios) {
radeon_atom_encoder_init(rdev); radeon_atom_encoder_init(rdev);

1
drivers/gpu/drm/radeon/radeon_fb.c
Unescape View File

@ -257,6 +257,7 @@ static int radeonfb_create(struct drm_fb_helper *helper,
} }
info->par = rfbdev; info->par = rfbdev;
info->skip_vt_switch = true;
ret = radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj); ret = radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
if (ret) { if (ret) {

12
drivers/gpu/drm/radeon/radeon_gem.c
Unescape View File

@ -428,7 +428,6 @@ int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp) struct drm_file *filp)
{ {
struct radeon_device *rdev = dev->dev_private;
struct drm_radeon_gem_busy *args = data; struct drm_radeon_gem_busy *args = data;
struct drm_gem_object *gobj; struct drm_gem_object *gobj;
struct radeon_bo *robj; struct radeon_bo *robj;
@ -440,10 +439,16 @@ int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
return -ENOENT; return -ENOENT;
} }
robj = gem_to_radeon_bo(gobj); robj = gem_to_radeon_bo(gobj);
r = radeon_bo_wait(robj, &cur_placement, true);
r = reservation_object_test_signaled_rcu(robj->tbo.resv, true);
if (r == 0)
r = -EBUSY;
else
r = 0;
cur_placement = ACCESS_ONCE(robj->tbo.mem.mem_type);
args->domain = radeon_mem_type_to_domain(cur_placement); args->domain = radeon_mem_type_to_domain(cur_placement);
drm_gem_object_unreference_unlocked(gobj); drm_gem_object_unreference_unlocked(gobj);
r = radeon_gem_handle_lockup(rdev, r);
return r; return r;
} }
@ -471,6 +476,7 @@ int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
r = ret; r = ret;
/* Flush HDP cache via MMIO if necessary */ /* Flush HDP cache via MMIO if necessary */
cur_placement = ACCESS_ONCE(robj->tbo.mem.mem_type);
if (rdev->asic->mmio_hdp_flush && if (rdev->asic->mmio_hdp_flush &&
radeon_mem_type_to_domain(cur_placement) == RADEON_GEM_DOMAIN_VRAM) radeon_mem_type_to_domain(cur_placement) == RADEON_GEM_DOMAIN_VRAM)
robj->rdev->asic->mmio_hdp_flush(rdev); robj->rdev->asic->mmio_hdp_flush(rdev);

1
drivers/gpu/drm/radeon/radeon_mode.h
Unescape View File

@ -343,7 +343,6 @@ struct radeon_crtc {
int max_cursor_width; int max_cursor_width;
int max_cursor_height; int max_cursor_height;
uint32_t legacy_display_base_addr; uint32_t legacy_display_base_addr;
uint32_t legacy_cursor_offset;
enum radeon_rmx_type rmx_type; enum radeon_rmx_type rmx_type;
u8 h_border; u8 h_border;
u8 v_border; u8 v_border;

40
drivers/gpu/drm/radeon/radeon_vm.c
Unescape View File

@ -493,38 +493,35 @@ int radeon_vm_bo_set_addr(struct radeon_device *rdev,
} }
if (bo_va->it.start || bo_va->it.last) { if (bo_va->it.start || bo_va->it.last) {
spin_lock(&vm->status_lock); /* add a clone of the bo_va to clear the old address */
if (list_empty(&bo_va->vm_status)) { struct radeon_bo_va *tmp;
/* add a clone of the bo_va to clear the old address */ tmp = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL);
struct radeon_bo_va *tmp; if (!tmp) {
spin_unlock(&vm->status_lock); mutex_unlock(&vm->mutex);
tmp = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL); r = -ENOMEM;
if (!tmp) { goto error_unreserve;
mutex_unlock(&vm->mutex);
r = -ENOMEM;
goto error_unreserve;
}
tmp->it.start = bo_va->it.start;
tmp->it.last = bo_va->it.last;
tmp->vm = vm;
tmp->bo = radeon_bo_ref(bo_va->bo);
spin_lock(&vm->status_lock);
list_add(&tmp->vm_status, &vm->freed);
} }
spin_unlock(&vm->status_lock); tmp->it.start = bo_va->it.start;
tmp->it.last = bo_va->it.last;
tmp->vm = vm;
tmp->bo = radeon_bo_ref(bo_va->bo);
interval_tree_remove(&bo_va->it, &vm->va); interval_tree_remove(&bo_va->it, &vm->va);
spin_lock(&vm->status_lock);
bo_va->it.start = 0; bo_va->it.start = 0;
bo_va->it.last = 0; bo_va->it.last = 0;
list_del_init(&bo_va->vm_status);
list_add(&tmp->vm_status, &vm->freed);
spin_unlock(&vm->status_lock);
} }
if (soffset || eoffset) { if (soffset || eoffset) {
spin_lock(&vm->status_lock);
bo_va->it.start = soffset; bo_va->it.start = soffset;
bo_va->it.last = eoffset - 1; bo_va->it.last = eoffset - 1;
interval_tree_insert(&bo_va->it, &vm->va);
spin_lock(&vm->status_lock);
list_add(&bo_va->vm_status, &vm->cleared); list_add(&bo_va->vm_status, &vm->cleared);
spin_unlock(&vm->status_lock); spin_unlock(&vm->status_lock);
interval_tree_insert(&bo_va->it, &vm->va);
} }
bo_va->flags = flags; bo_va->flags = flags;
@ -1158,7 +1155,8 @@ void radeon_vm_bo_invalidate(struct radeon_device *rdev,
list_for_each_entry(bo_va, &bo->va, bo_list) { list_for_each_entry(bo_va, &bo->va, bo_list) {
spin_lock(&bo_va->vm->status_lock); spin_lock(&bo_va->vm->status_lock);
if (list_empty(&bo_va->vm_status)) if (list_empty(&bo_va->vm_status) &&
(bo_va->it.start || bo_va->it.last))
list_add(&bo_va->vm_status, &bo_va->vm->invalidated); list_add(&bo_va->vm_status, &bo_va->vm->invalidated);
spin_unlock(&bo_va->vm->status_lock); spin_unlock(&bo_va->vm->status_lock);
} }

336
drivers/gpu/drm/radeon/si.c
Unescape View File

@ -6466,23 +6466,27 @@ restart_ih:
case 1: /* D1 vblank/vline */ case 1: /* D1 vblank/vline */
switch (src_data) { switch (src_data) {
case 0: /* D1 vblank */ case 0: /* D1 vblank */
if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT))
if (rdev->irq.crtc_vblank_int[0]) { DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
drm_handle_vblank(rdev->ddev, 0);
rdev->pm.vblank_sync = true; if (rdev->irq.crtc_vblank_int[0]) {
wake_up(&rdev->irq.vblank_queue); drm_handle_vblank(rdev->ddev, 0);
} rdev->pm.vblank_sync = true;
if (atomic_read(&rdev->irq.pflip[0])) wake_up(&rdev->irq.vblank_queue);
radeon_crtc_handle_vblank(rdev, 0);
rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D1 vblank\n");
} }
if (atomic_read(&rdev->irq.pflip[0]))
radeon_crtc_handle_vblank(rdev, 0);
rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D1 vblank\n");
break; break;
case 1: /* D1 vline */ case 1: /* D1 vline */
if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
DRM_DEBUG("IH: D1 vline\n");
} rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
DRM_DEBUG("IH: D1 vline\n");
break; break;
default: default:
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@ -6492,23 +6496,27 @@ restart_ih:
case 2: /* D2 vblank/vline */ case 2: /* D2 vblank/vline */
switch (src_data) { switch (src_data) {
case 0: /* D2 vblank */ case 0: /* D2 vblank */
if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT))
if (rdev->irq.crtc_vblank_int[1]) { DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
drm_handle_vblank(rdev->ddev, 1);
rdev->pm.vblank_sync = true; if (rdev->irq.crtc_vblank_int[1]) {
wake_up(&rdev->irq.vblank_queue); drm_handle_vblank(rdev->ddev, 1);
} rdev->pm.vblank_sync = true;
if (atomic_read(&rdev->irq.pflip[1])) wake_up(&rdev->irq.vblank_queue);
radeon_crtc_handle_vblank(rdev, 1);
rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D2 vblank\n");
} }
if (atomic_read(&rdev->irq.pflip[1]))
radeon_crtc_handle_vblank(rdev, 1);
rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D2 vblank\n");
break; break;
case 1: /* D2 vline */ case 1: /* D2 vline */
if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
DRM_DEBUG("IH: D2 vline\n");
} rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
DRM_DEBUG("IH: D2 vline\n");
break; break;
default: default:
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@ -6518,23 +6526,27 @@ restart_ih:
case 3: /* D3 vblank/vline */ case 3: /* D3 vblank/vline */
switch (src_data) { switch (src_data) {
case 0: /* D3 vblank */ case 0: /* D3 vblank */
if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT))
if (rdev->irq.crtc_vblank_int[2]) { DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
drm_handle_vblank(rdev->ddev, 2);
rdev->pm.vblank_sync = true; if (rdev->irq.crtc_vblank_int[2]) {
wake_up(&rdev->irq.vblank_queue); drm_handle_vblank(rdev->ddev, 2);
} rdev->pm.vblank_sync = true;
if (atomic_read(&rdev->irq.pflip[2])) wake_up(&rdev->irq.vblank_queue);
radeon_crtc_handle_vblank(rdev, 2);
rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D3 vblank\n");
} }
if (atomic_read(&rdev->irq.pflip[2]))
radeon_crtc_handle_vblank(rdev, 2);
rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D3 vblank\n");
break; break;
case 1: /* D3 vline */ case 1: /* D3 vline */
if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
DRM_DEBUG("IH: D3 vline\n");
} rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
DRM_DEBUG("IH: D3 vline\n");
break; break;
default: default:
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@ -6544,23 +6556,27 @@ restart_ih:
case 4: /* D4 vblank/vline */ case 4: /* D4 vblank/vline */
switch (src_data) { switch (src_data) {
case 0: /* D4 vblank */ case 0: /* D4 vblank */
if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT))
if (rdev->irq.crtc_vblank_int[3]) { DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
drm_handle_vblank(rdev->ddev, 3);
rdev->pm.vblank_sync = true; if (rdev->irq.crtc_vblank_int[3]) {
wake_up(&rdev->irq.vblank_queue); drm_handle_vblank(rdev->ddev, 3);
} rdev->pm.vblank_sync = true;
if (atomic_read(&rdev->irq.pflip[3])) wake_up(&rdev->irq.vblank_queue);
radeon_crtc_handle_vblank(rdev, 3);
rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D4 vblank\n");
} }
if (atomic_read(&rdev->irq.pflip[3]))
radeon_crtc_handle_vblank(rdev, 3);
rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D4 vblank\n");
break; break;
case 1: /* D4 vline */ case 1: /* D4 vline */
if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
DRM_DEBUG("IH: D4 vline\n");
} rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
DRM_DEBUG("IH: D4 vline\n");
break; break;
default: default:
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@ -6570,23 +6586,27 @@ restart_ih:
case 5: /* D5 vblank/vline */ case 5: /* D5 vblank/vline */
switch (src_data) { switch (src_data) {
case 0: /* D5 vblank */ case 0: /* D5 vblank */
if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT))
if (rdev->irq.crtc_vblank_int[4]) { DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
drm_handle_vblank(rdev->ddev, 4);
rdev->pm.vblank_sync = true; if (rdev->irq.crtc_vblank_int[4]) {
wake_up(&rdev->irq.vblank_queue); drm_handle_vblank(rdev->ddev, 4);
} rdev->pm.vblank_sync = true;
if (atomic_read(&rdev->irq.pflip[4])) wake_up(&rdev->irq.vblank_queue);
radeon_crtc_handle_vblank(rdev, 4);
rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D5 vblank\n");
} }
if (atomic_read(&rdev->irq.pflip[4]))
radeon_crtc_handle_vblank(rdev, 4);
rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D5 vblank\n");
break; break;
case 1: /* D5 vline */ case 1: /* D5 vline */
if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
DRM_DEBUG("IH: D5 vline\n");
} rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
DRM_DEBUG("IH: D5 vline\n");
break; break;
default: default:
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@ -6596,23 +6616,27 @@ restart_ih:
case 6: /* D6 vblank/vline */ case 6: /* D6 vblank/vline */
switch (src_data) { switch (src_data) {
case 0: /* D6 vblank */ case 0: /* D6 vblank */
if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT))
if (rdev->irq.crtc_vblank_int[5]) { DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
drm_handle_vblank(rdev->ddev, 5);
rdev->pm.vblank_sync = true; if (rdev->irq.crtc_vblank_int[5]) {
wake_up(&rdev->irq.vblank_queue); drm_handle_vblank(rdev->ddev, 5);
} rdev->pm.vblank_sync = true;
if (atomic_read(&rdev->irq.pflip[5])) wake_up(&rdev->irq.vblank_queue);
radeon_crtc_handle_vblank(rdev, 5);
rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D6 vblank\n");
} }
if (atomic_read(&rdev->irq.pflip[5]))
radeon_crtc_handle_vblank(rdev, 5);
rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D6 vblank\n");
break; break;
case 1: /* D6 vline */ case 1: /* D6 vline */
if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
DRM_DEBUG("IH: D6 vline\n");
} rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
DRM_DEBUG("IH: D6 vline\n");
break; break;
default: default:
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
@ -6632,88 +6656,112 @@ restart_ih:
case 42: /* HPD hotplug */ case 42: /* HPD hotplug */
switch (src_data) { switch (src_data) {
case 0: case 0:
if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_hotplug = true;
DRM_DEBUG("IH: HPD1\n"); rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
} queue_hotplug = true;
DRM_DEBUG("IH: HPD1\n");
break; break;
case 1: case 1:
if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_hotplug = true;
DRM_DEBUG("IH: HPD2\n"); rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
} queue_hotplug = true;
DRM_DEBUG("IH: HPD2\n");
break; break;
case 2: case 2:
if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_hotplug = true;
DRM_DEBUG("IH: HPD3\n"); rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
} queue_hotplug = true;
DRM_DEBUG("IH: HPD3\n");
break; break;
case 3: case 3:
if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_hotplug = true;
DRM_DEBUG("IH: HPD4\n"); rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
} queue_hotplug = true;
DRM_DEBUG("IH: HPD4\n");
break; break;
case 4: case 4:
if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_hotplug = true;
DRM_DEBUG("IH: HPD5\n"); rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
} queue_hotplug = true;
DRM_DEBUG("IH: HPD5\n");
break; break;
case 5: case 5:
if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_hotplug = true;
DRM_DEBUG("IH: HPD6\n"); rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
} queue_hotplug = true;
DRM_DEBUG("IH: HPD6\n");
break; break;
case 6: case 6:
if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_RX_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_dp = true;
DRM_DEBUG("IH: HPD_RX 1\n"); rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_RX_INTERRUPT;
} queue_dp = true;
DRM_DEBUG("IH: HPD_RX 1\n");
break; break;
case 7: case 7:
if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_dp = true;
DRM_DEBUG("IH: HPD_RX 2\n"); rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT;
} queue_dp = true;
DRM_DEBUG("IH: HPD_RX 2\n");
break; break;
case 8: case 8:
if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_dp = true;
DRM_DEBUG("IH: HPD_RX 3\n"); rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT;
} queue_dp = true;
DRM_DEBUG("IH: HPD_RX 3\n");
break; break;
case 9: case 9:
if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_dp = true;
DRM_DEBUG("IH: HPD_RX 4\n"); rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT;
} queue_dp = true;
DRM_DEBUG("IH: HPD_RX 4\n");
break; break;
case 10: case 10:
if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_dp = true;
DRM_DEBUG("IH: HPD_RX 5\n"); rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT;
} queue_dp = true;
DRM_DEBUG("IH: HPD_RX 5\n");
break; break;
case 11: case 11:
if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) { if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT))
rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT; DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
queue_dp = true;
DRM_DEBUG("IH: HPD_RX 6\n"); rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT;
} queue_dp = true;
DRM_DEBUG("IH: HPD_RX 6\n");
break; break;
default: default:
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);

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