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drm/i915/perf: prune OA configs

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In the following commit we'll introduce loadable userspace
configs. This change reworks how configurations are handled in the
perf driver and retains only the test configurations in kernel space.

We now store the test config in dev_priv and resolve the id only once
when opening the perf stream. The OA config is then handled through a
pointer to the structure holding the configuration details.

v2: Rework how test configs are handled (Lionel)

v3: Use u32 to hold number of register (Matthew)

v4: Removed unused dev_priv->perf.oa.current_config variable (Matthew)

v5: Lock device when accessing exclusive_stream (Lionel)

v6: Ensure OACTXCONTROL is always reprogrammed (Lionel)

v7: Switch a couple of index variable from int to u32 (Matthew)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170803165812.2373-3-lionel.g.landwerlin@intel.com
tirimbino
Lionel Landwerlin 8 years ago
parent 01d928e9a1
commit 701f8231a2
22 changed files with 509 additions and 29560 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 44
      drivers/gpu/drm/i915/i915_drv.h
  2. 5360
      drivers/gpu/drm/i915/i915_oa_bdw.c
  3. 8
      drivers/gpu/drm/i915/i915_oa_bdw.h
  4. 2623
      drivers/gpu/drm/i915/i915_oa_bxt.c
  5. 8
      drivers/gpu/drm/i915/i915_oa_bxt.h
  6. 2806
      drivers/gpu/drm/i915/i915_oa_chv.c
  7. 8
      drivers/gpu/drm/i915/i915_oa_chv.h
  8. 2535
      drivers/gpu/drm/i915/i915_oa_glk.c
  9. 8
      drivers/gpu/drm/i915/i915_oa_glk.h
  10. 764
      drivers/gpu/drm/i915/i915_oa_hsw.c
  11. 8
      drivers/gpu/drm/i915/i915_oa_hsw.h
  12. 2971
      drivers/gpu/drm/i915/i915_oa_kblgt2.c
  13. 8
      drivers/gpu/drm/i915/i915_oa_kblgt2.h
  14. 3020
      drivers/gpu/drm/i915/i915_oa_kblgt3.c
  15. 8
      drivers/gpu/drm/i915/i915_oa_kblgt3.h
  16. 3458
      drivers/gpu/drm/i915/i915_oa_sklgt2.c
  17. 8
      drivers/gpu/drm/i915/i915_oa_sklgt2.h
  18. 3019
      drivers/gpu/drm/i915/i915_oa_sklgt3.c
  19. 8
      drivers/gpu/drm/i915/i915_oa_sklgt3.h
  20. 3073
      drivers/gpu/drm/i915/i915_oa_sklgt4.c
  21. 8
      drivers/gpu/drm/i915/i915_oa_sklgt4.h
  22. 312
      drivers/gpu/drm/i915/i915_perf.c

44
drivers/gpu/drm/i915/i915_drv.h
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@ -1921,6 +1921,22 @@ struct i915_oa_reg {
u32 value;
};
struct i915_oa_config {
char uuid[UUID_STRING_LEN + 1];
int id;
const struct i915_oa_reg *mux_regs;
u32 mux_regs_len;
const struct i915_oa_reg *b_counter_regs;
u32 b_counter_regs_len;
const struct i915_oa_reg *flex_regs;
u32 flex_regs_len;
struct attribute_group sysfs_metric;
struct attribute *attrs[2];
struct device_attribute sysfs_metric_id;
};
struct i915_perf_stream;
/**
@ -2033,6 +2049,11 @@ struct i915_perf_stream {
* type of configured stream.
*/
const struct i915_perf_stream_ops *ops;
/**
* @oa_config: The OA configuration used by the stream.
*/
struct i915_oa_config *oa_config;
};
/**
@ -2056,21 +2077,14 @@ struct i915_oa_ops {
*/
void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
/**
* @select_metric_set: The auto generated code that checks whether a
* requested OA config is applicable to the system and if so sets up
* the mux, oa and flex eu register config pointers according to the
* current dev_priv->perf.oa.metrics_set.
*/
int (*select_metric_set)(struct drm_i915_private *dev_priv);
/**
* @enable_metric_set: Selects and applies any MUX configuration to set
* up the Boolean and Custom (B/C) counters that are part of the
* counter reports being sampled. May apply system constraints such as
* disabling EU clock gating as required.
*/
int (*enable_metric_set)(struct drm_i915_private *dev_priv);
int (*enable_metric_set)(struct drm_i915_private *dev_priv,
const struct i915_oa_config *oa_config);
/**
* @disable_metric_set: Remove system constraints associated with using
@ -2452,16 +2466,7 @@ struct drm_i915_private {
int period_exponent;
int timestamp_frequency;
int metrics_set;
const struct i915_oa_reg *mux_regs[6];
int mux_regs_lens[6];
int n_mux_configs;
const struct i915_oa_reg *b_counter_regs;
int b_counter_regs_len;
const struct i915_oa_reg *flex_regs;
int flex_regs_len;
struct i915_oa_config test_config;
struct {
struct i915_vma *vma;
@ -2548,7 +2553,6 @@ struct drm_i915_private {
struct i915_oa_ops ops;
const struct i915_oa_format *oa_formats;
int n_builtin_sets;
} oa;
} perf;

5360
drivers/gpu/drm/i915/i915_oa_bdw.c
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File diff suppressed because it is too large Load Diff

8
drivers/gpu/drm/i915/i915_oa_bdw.h
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@ -29,12 +29,6 @@
#ifndef __I915_OA_BDW_H__
#define __I915_OA_BDW_H__
extern int i915_oa_n_builtin_metric_sets_bdw;
extern int i915_oa_select_metric_set_bdw(struct drm_i915_private *dev_priv);
extern int i915_perf_register_sysfs_bdw(struct drm_i915_private *dev_priv);
extern void i915_perf_unregister_sysfs_bdw(struct drm_i915_private *dev_priv);
extern void i915_perf_load_test_config_bdw(struct drm_i915_private *dev_priv);
#endif

2623
drivers/gpu/drm/i915/i915_oa_bxt.c
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8
drivers/gpu/drm/i915/i915_oa_bxt.h
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@ -29,12 +29,6 @@
#ifndef __I915_OA_BXT_H__
#define __I915_OA_BXT_H__
extern int i915_oa_n_builtin_metric_sets_bxt;
extern int i915_oa_select_metric_set_bxt(struct drm_i915_private *dev_priv);
extern int i915_perf_register_sysfs_bxt(struct drm_i915_private *dev_priv);
extern void i915_perf_unregister_sysfs_bxt(struct drm_i915_private *dev_priv);
extern void i915_perf_load_test_config_bxt(struct drm_i915_private *dev_priv);
#endif

2806
drivers/gpu/drm/i915/i915_oa_chv.c
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8
drivers/gpu/drm/i915/i915_oa_chv.h
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@ -29,12 +29,6 @@
#ifndef __I915_OA_CHV_H__
#define __I915_OA_CHV_H__
extern int i915_oa_n_builtin_metric_sets_chv;
extern int i915_oa_select_metric_set_chv(struct drm_i915_private *dev_priv);
extern int i915_perf_register_sysfs_chv(struct drm_i915_private *dev_priv);
extern void i915_perf_unregister_sysfs_chv(struct drm_i915_private *dev_priv);
extern void i915_perf_load_test_config_chv(struct drm_i915_private *dev_priv);
#endif

2535
drivers/gpu/drm/i915/i915_oa_glk.c
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8
drivers/gpu/drm/i915/i915_oa_glk.h
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@ -29,12 +29,6 @@
#ifndef __I915_OA_GLK_H__
#define __I915_OA_GLK_H__
extern int i915_oa_n_builtin_metric_sets_glk;
extern int i915_oa_select_metric_set_glk(struct drm_i915_private *dev_priv);
extern int i915_perf_register_sysfs_glk(struct drm_i915_private *dev_priv);
extern void i915_perf_unregister_sysfs_glk(struct drm_i915_private *dev_priv);
extern void i915_perf_load_test_config_glk(struct drm_i915_private *dev_priv);
#endif

764
drivers/gpu/drm/i915/i915_oa_hsw.c
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@ -31,17 +31,6 @@
#include "i915_drv.h"
#include "i915_oa_hsw.h"
enum metric_set_id {
METRIC_SET_ID_RENDER_BASIC = 1,
METRIC_SET_ID_COMPUTE_BASIC,
METRIC_SET_ID_COMPUTE_EXTENDED,
METRIC_SET_ID_MEMORY_READS,
METRIC_SET_ID_MEMORY_WRITES,
METRIC_SET_ID_SAMPLER_BALANCE,
};
int i915_oa_n_builtin_metric_sets_hsw = 6;
static const struct i915_oa_reg b_counter_config_render_basic[] = {
{ _MMIO(0x2724), 0x00800000 },
{ _MMIO(0x2720), 0x00000000 },
@ -114,750 +103,35 @@ static const struct i915_oa_reg mux_config_render_basic[] = {
{ _MMIO(0x25428), 0x00042049 },
};
static int
get_render_basic_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_render_basic;
lens[n] = ARRAY_SIZE(mux_config_render_basic);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_compute_basic[] = {
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x00800000 },
{ _MMIO(0x2718), 0xaaaaaaaa },
{ _MMIO(0x271c), 0xaaaaaaaa },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
{ _MMIO(0x2728), 0xaaaaaaaa },
{ _MMIO(0x272c), 0xaaaaaaaa },
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00000000 },
{ _MMIO(0x2748), 0x00000000 },
{ _MMIO(0x274c), 0x00000000 },
{ _MMIO(0x2750), 0x00000000 },
{ _MMIO(0x2754), 0x00000000 },
{ _MMIO(0x2758), 0x00000000 },
{ _MMIO(0x275c), 0x00000000 },
{ _MMIO(0x236c), 0x00000000 },
};
static const struct i915_oa_reg flex_eu_config_compute_basic[] = {
};
static const struct i915_oa_reg mux_config_compute_basic[] = {
{ _MMIO(0x253a4), 0x00000000 },
{ _MMIO(0x2681c), 0x01f00800 },
{ _MMIO(0x26820), 0x00001000 },
{ _MMIO(0x2781c), 0x01f00800 },
{ _MMIO(0x26520), 0x00000007 },
{ _MMIO(0x265a0), 0x00000007 },
{ _MMIO(0x25380), 0x00000010 },
{ _MMIO(0x2538c), 0x00300000 },
{ _MMIO(0x25384), 0xaa8aaaaa },
{ _MMIO(0x25404), 0xffffffff },
{ _MMIO(0x26800), 0x00004202 },
{ _MMIO(0x26808), 0x00605817 },
{ _MMIO(0x2680c), 0x10001005 },
{ _MMIO(0x26804), 0x00000000 },
{ _MMIO(0x27800), 0x00000102 },
{ _MMIO(0x27808), 0x0c0701e0 },
{ _MMIO(0x2780c), 0x000200a0 },
{ _MMIO(0x27804), 0x00000000 },
{ _MMIO(0x26484), 0x44000000 },
{ _MMIO(0x26704), 0x44000000 },
{ _MMIO(0x26500), 0x00000006 },
{ _MMIO(0x26510), 0x00000001 },
{ _MMIO(0x26504), 0x88000000 },
{ _MMIO(0x26580), 0x00000006 },
{ _MMIO(0x26590), 0x00000020 },
{ _MMIO(0x26584), 0x00000000 },
{ _MMIO(0x26104), 0x55822222 },
{ _MMIO(0x26184), 0xaa866666 },
{ _MMIO(0x25420), 0x08320c83 },
{ _MMIO(0x25424), 0x06820c83 },
{ _MMIO(0x2541c), 0x00000000 },
{ _MMIO(0x25428), 0x00000c03 },
};
static int
get_compute_basic_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_compute_basic;
lens[n] = ARRAY_SIZE(mux_config_compute_basic);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_compute_extended[] = {
{ _MMIO(0x2724), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2770), 0x0007fe2a },
{ _MMIO(0x2774), 0x0000ff00 },
{ _MMIO(0x2778), 0x0007fe6a },
{ _MMIO(0x277c), 0x0000ff00 },
{ _MMIO(0x2780), 0x0007fe92 },
{ _MMIO(0x2784), 0x0000ff00 },
{ _MMIO(0x2788), 0x0007fea2 },
{ _MMIO(0x278c), 0x0000ff00 },
{ _MMIO(0x2790), 0x0007fe32 },
{ _MMIO(0x2794), 0x0000ff00 },
{ _MMIO(0x2798), 0x0007fe9a },
{ _MMIO(0x279c), 0x0000ff00 },
{ _MMIO(0x27a0), 0x0007ff23 },
{ _MMIO(0x27a4), 0x0000ff00 },
{ _MMIO(0x27a8), 0x0007fff3 },
{ _MMIO(0x27ac), 0x0000fffe },
};
static const struct i915_oa_reg flex_eu_config_compute_extended[] = {
};
static const struct i915_oa_reg mux_config_compute_extended[] = {
{ _MMIO(0x2681c), 0x3eb00800 },
{ _MMIO(0x26820), 0x00900000 },
{ _MMIO(0x25384), 0x02aaaaaa },
{ _MMIO(0x25404), 0x03ffffff },
{ _MMIO(0x26800), 0x00142284 },
{ _MMIO(0x26808), 0x0e629062 },
{ _MMIO(0x2680c), 0x3f6f55cb },
{ _MMIO(0x26810), 0x00000014 },
{ _MMIO(0x26804), 0x00000000 },
{ _MMIO(0x26104), 0x02aaaaaa },
{ _MMIO(0x26184), 0x02aaaaaa },
{ _MMIO(0x25420), 0x00000000 },
{ _MMIO(0x25424), 0x00000000 },
{ _MMIO(0x2541c), 0x00000000 },
{ _MMIO(0x25428), 0x00000000 },
};
static int
get_compute_extended_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_compute_extended;
lens[n] = ARRAY_SIZE(mux_config_compute_extended);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_memory_reads[] = {
{ _MMIO(0x2724), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x274c), 0x76543298 },
{ _MMIO(0x2748), 0x98989898 },
{ _MMIO(0x2744), 0x000000e4 },
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x275c), 0x98a98a98 },
{ _MMIO(0x2758), 0x88888888 },
{ _MMIO(0x2754), 0x000c5500 },
{ _MMIO(0x2750), 0x00000000 },
{ _MMIO(0x2770), 0x0007f81a },
{ _MMIO(0x2774), 0x0000fc00 },
{ _MMIO(0x2778), 0x0007f82a },
{ _MMIO(0x277c), 0x0000fc00 },
{ _MMIO(0x2780), 0x0007f872 },
{ _MMIO(0x2784), 0x0000fc00 },
{ _MMIO(0x2788), 0x0007f8ba },
{ _MMIO(0x278c), 0x0000fc00 },
{ _MMIO(0x2790), 0x0007f87a },
{ _MMIO(0x2794), 0x0000fc00 },
{ _MMIO(0x2798), 0x0007f8ea },
{ _MMIO(0x279c), 0x0000fc00 },
{ _MMIO(0x27a0), 0x0007f8e2 },
{ _MMIO(0x27a4), 0x0000fc00 },
{ _MMIO(0x27a8), 0x0007f8f2 },
{ _MMIO(0x27ac), 0x0000fc00 },
};
static const struct i915_oa_reg flex_eu_config_memory_reads[] = {
};
static const struct i915_oa_reg mux_config_memory_reads[] = {
{ _MMIO(0x253a4), 0x34300000 },
{ _MMIO(0x25440), 0x2d800000 },
{ _MMIO(0x25444), 0x00000008 },
{ _MMIO(0x25128), 0x0e600000 },
{ _MMIO(0x25380), 0x00000450 },
{ _MMIO(0x25390), 0x00052c43 },
{ _MMIO(0x25384), 0x00000000 },
{ _MMIO(0x25400), 0x00006144 },
{ _MMIO(0x25408), 0x0a418820 },
{ _MMIO(0x2540c), 0x000820e6 },
{ _MMIO(0x25404), 0xff500000 },
{ _MMIO(0x25100), 0x000005d6 },
{ _MMIO(0x2510c), 0x0ef00000 },
{ _MMIO(0x25104), 0x00000000 },
{ _MMIO(0x25420), 0x02108421 },
{ _MMIO(0x25424), 0x00008421 },
{ _MMIO(0x2541c), 0x00000000 },
{ _MMIO(0x25428), 0x00000000 },
};
static int
get_memory_reads_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_memory_reads;
lens[n] = ARRAY_SIZE(mux_config_memory_reads);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_memory_writes[] = {
{ _MMIO(0x2724), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x274c), 0x76543298 },
{ _MMIO(0x2748), 0x98989898 },
{ _MMIO(0x2744), 0x000000e4 },
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x275c), 0xbabababa },
{ _MMIO(0x2758), 0x88888888 },
{ _MMIO(0x2754), 0x000c5500 },
{ _MMIO(0x2750), 0x00000000 },
{ _MMIO(0x2770), 0x0007f81a },
{ _MMIO(0x2774), 0x0000fc00 },
{ _MMIO(0x2778), 0x0007f82a },
{ _MMIO(0x277c), 0x0000fc00 },
{ _MMIO(0x2780), 0x0007f822 },
{ _MMIO(0x2784), 0x0000fc00 },
{ _MMIO(0x2788), 0x0007f8ba },
{ _MMIO(0x278c), 0x0000fc00 },
{ _MMIO(0x2790), 0x0007f87a },
{ _MMIO(0x2794), 0x0000fc00 },
{ _MMIO(0x2798), 0x0007f8ea },
{ _MMIO(0x279c), 0x0000fc00 },
{ _MMIO(0x27a0), 0x0007f8e2 },
{ _MMIO(0x27a4), 0x0000fc00 },
{ _MMIO(0x27a8), 0x0007f8f2 },
{ _MMIO(0x27ac), 0x0000fc00 },
};
static const struct i915_oa_reg flex_eu_config_memory_writes[] = {
};
static const struct i915_oa_reg mux_config_memory_writes[] = {
{ _MMIO(0x253a4), 0x34300000 },
{ _MMIO(0x25440), 0x01500000 },
{ _MMIO(0x25444), 0x00000120 },
{ _MMIO(0x25128), 0x0c200000 },
{ _MMIO(0x25380), 0x00000450 },
{ _MMIO(0x25390), 0x00052c43 },
{ _MMIO(0x25384), 0x00000000 },
{ _MMIO(0x25400), 0x00007184 },
{ _MMIO(0x25408), 0x0a418820 },
{ _MMIO(0x2540c), 0x000820e6 },
{ _MMIO(0x25404), 0xff500000 },
{ _MMIO(0x25100), 0x000005d6 },
{ _MMIO(0x2510c), 0x1e700000 },
{ _MMIO(0x25104), 0x00000000 },
{ _MMIO(0x25420), 0x02108421 },
{ _MMIO(0x25424), 0x00008421 },
{ _MMIO(0x2541c), 0x00000000 },
{ _MMIO(0x25428), 0x00000000 },
};
static int
get_memory_writes_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_memory_writes;
lens[n] = ARRAY_SIZE(mux_config_memory_writes);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_sampler_balance[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x00800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
};
static const struct i915_oa_reg flex_eu_config_sampler_balance[] = {
};
static const struct i915_oa_reg mux_config_sampler_balance[] = {
{ _MMIO(0x2eb9c), 0x01906400 },
{ _MMIO(0x2fb9c), 0x01906400 },
{ _MMIO(0x253a4), 0x00000000 },
{ _MMIO(0x26b9c), 0x01906400 },
{ _MMIO(0x27b9c), 0x01906400 },
{ _MMIO(0x27104), 0x00a00000 },
{ _MMIO(0x27184), 0x00a50000 },
{ _MMIO(0x2e804), 0x00500000 },
{ _MMIO(0x2e984), 0x00500000 },
{ _MMIO(0x2eb04), 0x00500000 },
{ _MMIO(0x2eb80), 0x00000084 },
{ _MMIO(0x2eb8c), 0x14200000 },
{ _MMIO(0x2eb84), 0x00000000 },
{ _MMIO(0x2f804), 0x00050000 },
{ _MMIO(0x2f984), 0x00050000 },
{ _MMIO(0x2fb04), 0x00050000 },
{ _MMIO(0x2fb80), 0x00000084 },
{ _MMIO(0x2fb8c), 0x00050800 },
{ _MMIO(0x2fb84), 0x00000000 },
{ _MMIO(0x25380), 0x00000010 },
{ _MMIO(0x2538c), 0x000000c0 },
{ _MMIO(0x25384), 0xaa550000 },
{ _MMIO(0x25404), 0xffffc000 },
{ _MMIO(0x26804), 0x50000000 },
{ _MMIO(0x26984), 0x50000000 },
{ _MMIO(0x26b04), 0x50000000 },
{ _MMIO(0x26b80), 0x00000084 },
{ _MMIO(0x26b90), 0x00050800 },
{ _MMIO(0x26b84), 0x00000000 },
{ _MMIO(0x27804), 0x05000000 },
{ _MMIO(0x27984), 0x05000000 },
{ _MMIO(0x27b04), 0x05000000 },
{ _MMIO(0x27b80), 0x00000084 },
{ _MMIO(0x27b90), 0x00000142 },
{ _MMIO(0x27b84), 0x00000000 },
{ _MMIO(0x26104), 0xa0000000 },
{ _MMIO(0x26184), 0xa5000000 },
{ _MMIO(0x25424), 0x00008620 },
{ _MMIO(0x2541c), 0x00000000 },
{ _MMIO(0x25428), 0x0004a54a },
};
static int
get_sampler_balance_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_sampler_balance;
lens[n] = ARRAY_SIZE(mux_config_sampler_balance);
n++;
return n;
}
int i915_oa_select_metric_set_hsw(struct drm_i915_private *dev_priv)
{
dev_priv->perf.oa.n_mux_configs = 0;
dev_priv->perf.oa.b_counter_regs = NULL;
dev_priv->perf.oa.b_counter_regs_len = 0;
switch (dev_priv->perf.oa.metrics_set) {
case METRIC_SET_ID_RENDER_BASIC:
dev_priv->perf.oa.n_mux_configs =
get_render_basic_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_render_basic;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_render_basic);
dev_priv->perf.oa.flex_regs =
flex_eu_config_render_basic;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_render_basic);
return 0;
case METRIC_SET_ID_COMPUTE_BASIC:
dev_priv->perf.oa.n_mux_configs =
get_compute_basic_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_compute_basic;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_compute_basic);
dev_priv->perf.oa.flex_regs =
flex_eu_config_compute_basic;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_compute_basic);
return 0;
case METRIC_SET_ID_COMPUTE_EXTENDED:
dev_priv->perf.oa.n_mux_configs =
get_compute_extended_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_compute_extended;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_compute_extended);
dev_priv->perf.oa.flex_regs =
flex_eu_config_compute_extended;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_compute_extended);
return 0;
case METRIC_SET_ID_MEMORY_READS:
dev_priv->perf.oa.n_mux_configs =
get_memory_reads_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_memory_reads;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_memory_reads);
dev_priv->perf.oa.flex_regs =
flex_eu_config_memory_reads;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_memory_reads);
return 0;
case METRIC_SET_ID_MEMORY_WRITES:
dev_priv->perf.oa.n_mux_configs =
get_memory_writes_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_memory_writes;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_memory_writes);
dev_priv->perf.oa.flex_regs =
flex_eu_config_memory_writes;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_memory_writes);
return 0;
case METRIC_SET_ID_SAMPLER_BALANCE:
dev_priv->perf.oa.n_mux_configs =
get_sampler_balance_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_BALANCE\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_sampler_balance;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_sampler_balance);
dev_priv->perf.oa.flex_regs =
flex_eu_config_sampler_balance;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_sampler_balance);
return 0;
default:
return -ENODEV;
}
}
static ssize_t
show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC);
return sprintf(buf, "1\n");
}
static struct device_attribute dev_attr_render_basic_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_render_basic_id,
.store = NULL,
};
static struct attribute *attrs_render_basic[] = {
&dev_attr_render_basic_id.attr,
NULL,
};
static struct attribute_group group_render_basic = {
.name = "403d8832-1a27-4aa6-a64e-f5389ce7b212",
.attrs = attrs_render_basic,
};
static ssize_t
show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC);
}
static struct device_attribute dev_attr_compute_basic_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_compute_basic_id,
.store = NULL,
};
static struct attribute *attrs_compute_basic[] = {
&dev_attr_compute_basic_id.attr,
NULL,
};
static struct attribute_group group_compute_basic = {
.name = "39ad14bc-2380-45c4-91eb-fbcb3aa7ae7b",
.attrs = attrs_compute_basic,
};
static ssize_t
show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED);
}
static struct device_attribute dev_attr_compute_extended_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_compute_extended_id,
.store = NULL,
};
static struct attribute *attrs_compute_extended[] = {
&dev_attr_compute_extended_id.attr,
NULL,
};
static struct attribute_group group_compute_extended = {
.name = "3865be28-6982-49fe-9494-e4d1b4795413",
.attrs = attrs_compute_extended,
};
static ssize_t
show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS);
}
static struct device_attribute dev_attr_memory_reads_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_memory_reads_id,
.store = NULL,
};
static struct attribute *attrs_memory_reads[] = {
&dev_attr_memory_reads_id.attr,
NULL,
};
static struct attribute_group group_memory_reads = {
.name = "bb5ed49b-2497-4095-94f6-26ba294db88a",
.attrs = attrs_memory_reads,
};
static ssize_t
show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf)
void
i915_perf_load_test_config_hsw(struct drm_i915_private *dev_priv)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES);
}
strncpy(dev_priv->perf.oa.test_config.uuid,
"403d8832-1a27-4aa6-a64e-f5389ce7b212",
UUID_STRING_LEN);
dev_priv->perf.oa.test_config.id = 1;
static struct device_attribute dev_attr_memory_writes_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_memory_writes_id,
.store = NULL,
};
static struct attribute *attrs_memory_writes[] = {
&dev_attr_memory_writes_id.attr,
NULL,
};
dev_priv->perf.oa.test_config.mux_regs = mux_config_render_basic;
dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_render_basic);
static struct attribute_group group_memory_writes = {
.name = "3358d639-9b5f-45ab-976d-9b08cbfc6240",
.attrs = attrs_memory_writes,
};
dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_render_basic;
dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_render_basic);
static ssize_t
show_sampler_balance_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_BALANCE);
}
dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_render_basic;
dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_render_basic);
static struct device_attribute dev_attr_sampler_balance_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_sampler_balance_id,
.store = NULL,
};
dev_priv->perf.oa.test_config.sysfs_metric.name = "403d8832-1a27-4aa6-a64e-f5389ce7b212";
dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
static struct attribute *attrs_sampler_balance[] = {
&dev_attr_sampler_balance_id.attr,
NULL,
};
static struct attribute_group group_sampler_balance = {
.name = "bc274488-b4b6-40c7-90da-b77d7ad16189",
.attrs = attrs_sampler_balance,
};
int
i915_perf_register_sysfs_hsw(struct drm_i915_private *dev_priv)
{
const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
int ret = 0;
if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic);
if (ret)
goto error_render_basic;
}
if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
if (ret)
goto error_compute_basic;
}
if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
if (ret)
goto error_compute_extended;
}
if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
if (ret)
goto error_memory_reads;
}
if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
if (ret)
goto error_memory_writes;
}
if (get_sampler_balance_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_balance);
if (ret)
goto error_sampler_balance;
}
return 0;
error_sampler_balance:
if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
error_memory_writes:
if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
error_memory_reads:
if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
error_compute_extended:
if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
error_compute_basic:
if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
error_render_basic:
return ret;
}
void
i915_perf_unregister_sysfs_hsw(struct drm_i915_private *dev_priv)
{
const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
if (get_sampler_balance_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_balance);
dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_render_basic_id;
}

8
drivers/gpu/drm/i915/i915_oa_hsw.h
Unescape View File

@ -29,12 +29,6 @@
#ifndef __I915_OA_HSW_H__
#define __I915_OA_HSW_H__
extern int i915_oa_n_builtin_metric_sets_hsw;
extern int i915_oa_select_metric_set_hsw(struct drm_i915_private *dev_priv);
extern int i915_perf_register_sysfs_hsw(struct drm_i915_private *dev_priv);
extern void i915_perf_unregister_sysfs_hsw(struct drm_i915_private *dev_priv);
extern void i915_perf_load_test_config_hsw(struct drm_i915_private *dev_priv);
#endif

2971
drivers/gpu/drm/i915/i915_oa_kblgt2.c
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File diff suppressed because it is too large Load Diff

8
drivers/gpu/drm/i915/i915_oa_kblgt2.h
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@ -29,12 +29,6 @@
#ifndef __I915_OA_KBLGT2_H__
#define __I915_OA_KBLGT2_H__
extern int i915_oa_n_builtin_metric_sets_kblgt2;
extern int i915_oa_select_metric_set_kblgt2(struct drm_i915_private *dev_priv);
extern int i915_perf_register_sysfs_kblgt2(struct drm_i915_private *dev_priv);
extern void i915_perf_unregister_sysfs_kblgt2(struct drm_i915_private *dev_priv);
extern void i915_perf_load_test_config_kblgt2(struct drm_i915_private *dev_priv);
#endif

3020
drivers/gpu/drm/i915/i915_oa_kblgt3.c
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8
drivers/gpu/drm/i915/i915_oa_kblgt3.h
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@ -29,12 +29,6 @@
#ifndef __I915_OA_KBLGT3_H__
#define __I915_OA_KBLGT3_H__
extern int i915_oa_n_builtin_metric_sets_kblgt3;
extern int i915_oa_select_metric_set_kblgt3(struct drm_i915_private *dev_priv);
extern int i915_perf_register_sysfs_kblgt3(struct drm_i915_private *dev_priv);
extern void i915_perf_unregister_sysfs_kblgt3(struct drm_i915_private *dev_priv);
extern void i915_perf_load_test_config_kblgt3(struct drm_i915_private *dev_priv);
#endif

3458
drivers/gpu/drm/i915/i915_oa_sklgt2.c
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8
drivers/gpu/drm/i915/i915_oa_sklgt2.h
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@ -29,12 +29,6 @@
#ifndef __I915_OA_SKLGT2_H__
#define __I915_OA_SKLGT2_H__
extern int i915_oa_n_builtin_metric_sets_sklgt2;
extern int i915_oa_select_metric_set_sklgt2(struct drm_i915_private *dev_priv);
extern int i915_perf_register_sysfs_sklgt2(struct drm_i915_private *dev_priv);
extern void i915_perf_unregister_sysfs_sklgt2(struct drm_i915_private *dev_priv);
extern void i915_perf_load_test_config_sklgt2(struct drm_i915_private *dev_priv);
#endif

3019
drivers/gpu/drm/i915/i915_oa_sklgt3.c
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8
drivers/gpu/drm/i915/i915_oa_sklgt3.h
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@ -29,12 +29,6 @@
#ifndef __I915_OA_SKLGT3_H__
#define __I915_OA_SKLGT3_H__
extern int i915_oa_n_builtin_metric_sets_sklgt3;
extern int i915_oa_select_metric_set_sklgt3(struct drm_i915_private *dev_priv);
extern int i915_perf_register_sysfs_sklgt3(struct drm_i915_private *dev_priv);
extern void i915_perf_unregister_sysfs_sklgt3(struct drm_i915_private *dev_priv);
extern void i915_perf_load_test_config_sklgt3(struct drm_i915_private *dev_priv);
#endif

3073
drivers/gpu/drm/i915/i915_oa_sklgt4.c
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8
drivers/gpu/drm/i915/i915_oa_sklgt4.h
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@ -29,12 +29,6 @@
#ifndef __I915_OA_SKLGT4_H__
#define __I915_OA_SKLGT4_H__
extern int i915_oa_n_builtin_metric_sets_sklgt4;
extern int i915_oa_select_metric_set_sklgt4(struct drm_i915_private *dev_priv);
extern int i915_perf_register_sysfs_sklgt4(struct drm_i915_private *dev_priv);
extern void i915_perf_unregister_sysfs_sklgt4(struct drm_i915_private *dev_priv);
extern void i915_perf_load_test_config_sklgt4(struct drm_i915_private *dev_priv);
#endif

312
drivers/gpu/drm/i915/i915_perf.c
Unescape View File

@ -1249,7 +1249,9 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
* Unset exclusive_stream first, it might be checked while
* disabling the metric set on gen8+.
*/
mutex_lock(&dev_priv->drm.struct_mutex);
dev_priv->perf.oa.exclusive_stream = NULL;
mutex_unlock(&dev_priv->drm.struct_mutex);
dev_priv->perf.oa.ops.disable_metric_set(dev_priv);
@ -1440,9 +1442,9 @@ unlock:
static void config_oa_regs(struct drm_i915_private *dev_priv,
const struct i915_oa_reg *regs,
int n_regs)
u32 n_regs)
{
int i;
u32 i;
for (i = 0; i < n_regs; i++) {
const struct i915_oa_reg *reg = regs + i;
@ -1451,14 +1453,9 @@ static void config_oa_regs(struct drm_i915_private *dev_priv,
}
}
static int hsw_enable_metric_set(struct drm_i915_private *dev_priv)
static int hsw_enable_metric_set(struct drm_i915_private *dev_priv,
const struct i915_oa_config *oa_config)
{
int ret = i915_oa_select_metric_set_hsw(dev_priv);
int i;
if (ret)
return ret;
I915_WRITE(GDT_CHICKEN_BITS, (I915_READ(GDT_CHICKEN_BITS) |
GT_NOA_ENABLE));
@ -1476,10 +1473,7 @@ static int hsw_enable_metric_set(struct drm_i915_private *dev_priv)
I915_WRITE(GEN6_UCGCTL1, (I915_READ(GEN6_UCGCTL1) |
GEN6_CSUNIT_CLOCK_GATE_DISABLE));
for (i = 0; i < dev_priv->perf.oa.n_mux_configs; i++) {
config_oa_regs(dev_priv, dev_priv->perf.oa.mux_regs[i],
dev_priv->perf.oa.mux_regs_lens[i]);
}
config_oa_regs(dev_priv, oa_config->mux_regs, oa_config->mux_regs_len);
/* It apparently takes a fairly long time for a new MUX
* configuration to be be applied after these register writes.
@ -1504,8 +1498,8 @@ static int hsw_enable_metric_set(struct drm_i915_private *dev_priv)
*/
usleep_range(15000, 20000);
config_oa_regs(dev_priv, dev_priv->perf.oa.b_counter_regs,
dev_priv->perf.oa.b_counter_regs_len);
config_oa_regs(dev_priv, oa_config->b_counter_regs,
oa_config->b_counter_regs_len);
return 0;
}
@ -1529,11 +1523,10 @@ static void hsw_disable_metric_set(struct drm_i915_private *dev_priv)
* in the case that the OA unit has been disabled.
*/
static void gen8_update_reg_state_unlocked(struct i915_gem_context *ctx,
u32 *reg_state)
u32 *reg_state,
const struct i915_oa_config *oa_config)
{
struct drm_i915_private *dev_priv = ctx->i915;
const struct i915_oa_reg *flex_regs = dev_priv->perf.oa.flex_regs;
int n_flex_regs = dev_priv->perf.oa.flex_regs_len;
u32 ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_offset;
u32 ctx_flexeu0 = dev_priv->perf.oa.ctx_flexeu0_offset;
/* The MMIO offsets for Flex EU registers aren't contiguous */
@ -1565,14 +1558,17 @@ static void gen8_update_reg_state_unlocked(struct i915_gem_context *ctx,
* will be an explicit 'No Event' we can select, but not yet...
*/
u32 value = 0;
int j;
for (j = 0; j < n_flex_regs; j++) {
if (i915_mmio_reg_offset(flex_regs[j].addr) == mmio) {
value = flex_regs[j].value;
if (oa_config) {
u32 j;
for (j = 0; j < oa_config->flex_regs_len; j++) {
if (i915_mmio_reg_offset(oa_config->flex_regs[j].addr) == mmio) {
value = oa_config->flex_regs[j].value;
break;
}
}
}
reg_state[state_offset] = mmio;
reg_state[state_offset+1] = value;
@ -1583,11 +1579,10 @@ static void gen8_update_reg_state_unlocked(struct i915_gem_context *ctx,
* Same as gen8_update_reg_state_unlocked only through the batchbuffer. This
* is only used by the kernel context.
*/
static int gen8_emit_oa_config(struct drm_i915_gem_request *req)
static int gen8_emit_oa_config(struct drm_i915_gem_request *req,
const struct i915_oa_config *oa_config)
{
struct drm_i915_private *dev_priv = req->i915;
const struct i915_oa_reg *flex_regs = dev_priv->perf.oa.flex_regs;
int n_flex_regs = dev_priv->perf.oa.flex_regs_len;
/* The MMIO offsets for Flex EU registers aren't contiguous */
u32 flex_mmio[] = {
i915_mmio_reg_offset(EU_PERF_CNTL0),
@ -1622,14 +1617,17 @@ static int gen8_emit_oa_config(struct drm_i915_gem_request *req)
* yet...
*/
u32 value = 0;
int j;
for (j = 0; j < n_flex_regs; j++) {
if (i915_mmio_reg_offset(flex_regs[j].addr) == mmio) {
value = flex_regs[j].value;
if (oa_config) {
u32 j;
for (j = 0; j < oa_config->flex_regs_len; j++) {
if (i915_mmio_reg_offset(oa_config->flex_regs[j].addr) == mmio) {
value = oa_config->flex_regs[j].value;
break;
}
}
}
*cs++ = mmio;
*cs++ = value;
@ -1641,7 +1639,8 @@ static int gen8_emit_oa_config(struct drm_i915_gem_request *req)
return 0;
}
static int gen8_switch_to_updated_kernel_context(struct drm_i915_private *dev_priv)
static int gen8_switch_to_updated_kernel_context(struct drm_i915_private *dev_priv,
const struct i915_oa_config *oa_config)
{
struct intel_engine_cs *engine = dev_priv->engine[RCS];
struct i915_gem_timeline *timeline;
@ -1656,7 +1655,7 @@ static int gen8_switch_to_updated_kernel_context(struct drm_i915_private *dev_pr
if (IS_ERR(req))
return PTR_ERR(req);
ret = gen8_emit_oa_config(req);
ret = gen8_emit_oa_config(req, oa_config);
if (ret) {
i915_add_request(req);
return ret;
@ -1707,6 +1706,7 @@ static int gen8_switch_to_updated_kernel_context(struct drm_i915_private *dev_pr
* Note: it's only the RCS/Render context that has any OA state.
*/
static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv,
const struct i915_oa_config *oa_config,
bool interruptible)
{
struct i915_gem_context *ctx;
@ -1724,7 +1724,7 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv,
}
/* Switch away from any user context. */
ret = gen8_switch_to_updated_kernel_context(dev_priv);
ret = gen8_switch_to_updated_kernel_context(dev_priv, oa_config);
if (ret)
goto out;
@ -1763,7 +1763,7 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv,
ce->state->obj->mm.dirty = true;
regs += LRC_STATE_PN * PAGE_SIZE / sizeof(*regs);
gen8_update_reg_state_unlocked(ctx, regs);
gen8_update_reg_state_unlocked(ctx, regs, oa_config);
i915_gem_object_unpin_map(ce->state->obj);
}
@ -1774,13 +1774,10 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv,
return ret;
}
static int gen8_enable_metric_set(struct drm_i915_private *dev_priv)
static int gen8_enable_metric_set(struct drm_i915_private *dev_priv,
const struct i915_oa_config *oa_config)
{
int ret = dev_priv->perf.oa.ops.select_metric_set(dev_priv);
int i;
if (ret)
return ret;
int ret;
/*
* We disable slice/unslice clock ratio change reports on SKL since
@ -1817,19 +1814,18 @@ static int gen8_enable_metric_set(struct drm_i915_private *dev_priv)
* to make sure all slices/subslices are ON before writing to NOA
* registers.
*/
ret = gen8_configure_all_contexts(dev_priv, true);
ret = gen8_configure_all_contexts(dev_priv, oa_config, true);
if (ret)
return ret;
I915_WRITE(GDT_CHICKEN_BITS, 0xA0);
for (i = 0; i < dev_priv->perf.oa.n_mux_configs; i++) {
config_oa_regs(dev_priv, dev_priv->perf.oa.mux_regs[i],
dev_priv->perf.oa.mux_regs_lens[i]);
}
config_oa_regs(dev_priv, oa_config->mux_regs, oa_config->mux_regs_len);
I915_WRITE(GDT_CHICKEN_BITS, 0x80);
config_oa_regs(dev_priv, dev_priv->perf.oa.b_counter_regs,
dev_priv->perf.oa.b_counter_regs_len);
config_oa_regs(dev_priv, oa_config->b_counter_regs,
oa_config->b_counter_regs_len);
return 0;
}
@ -1837,7 +1833,7 @@ static int gen8_enable_metric_set(struct drm_i915_private *dev_priv)
static void gen8_disable_metric_set(struct drm_i915_private *dev_priv)
{
/* Reset all contexts' slices/subslices configurations. */
gen8_configure_all_contexts(dev_priv, false);
gen8_configure_all_contexts(dev_priv, NULL, false);
}
static void gen7_oa_enable(struct drm_i915_private *dev_priv)
@ -1957,6 +1953,15 @@ static const struct i915_perf_stream_ops i915_oa_stream_ops = {
.read = i915_oa_read,
};
static struct i915_oa_config *get_oa_config(struct drm_i915_private *dev_priv,
int metrics_set)
{
if (metrics_set == 1)
return &dev_priv->perf.oa.test_config;
return NULL;
}
/**
* i915_oa_stream_init - validate combined props for OA stream and init
* @stream: An i915 perf stream
@ -2011,11 +2016,6 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
return -EBUSY;
}
if (!props->metrics_set) {
DRM_DEBUG("OA metric set not specified\n");
return -EINVAL;
}
if (!props->oa_format) {
DRM_DEBUG("OA report format not specified\n");
return -EINVAL;
@ -2055,8 +2055,6 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
dev_priv->perf.oa.oa_buffer.format =
dev_priv->perf.oa.oa_formats[props->oa_format].format;
dev_priv->perf.oa.metrics_set = props->metrics_set;
dev_priv->perf.oa.periodic = props->oa_periodic;
if (dev_priv->perf.oa.periodic)
dev_priv->perf.oa.period_exponent = props->oa_period_exponent;
@ -2067,6 +2065,10 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
return ret;
}
stream->oa_config = get_oa_config(dev_priv, props->metrics_set);
if (!stream->oa_config)
return -EINVAL;
/* PRM - observability performance counters:
*
* OACONTROL, performance counter enable, note:
@ -2086,16 +2088,29 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
if (ret)
goto err_oa_buf_alloc;
ret = dev_priv->perf.oa.ops.enable_metric_set(dev_priv);
ret = dev_priv->perf.oa.ops.enable_metric_set(dev_priv,
stream->oa_config);
if (ret)
goto err_enable;
stream->ops = &i915_oa_stream_ops;
/* Lock device for exclusive_stream access late because
* enable_metric_set() might lock as well on gen8+.
*/
ret = i915_mutex_lock_interruptible(&dev_priv->drm);
if (ret)
goto err_lock;
dev_priv->perf.oa.exclusive_stream = stream;
mutex_unlock(&dev_priv->drm.struct_mutex);
return 0;
err_lock:
dev_priv->perf.oa.ops.disable_metric_set(dev_priv);
err_enable:
free_oa_buffer(dev_priv);
@ -2113,6 +2128,7 @@ void i915_oa_init_reg_state(struct intel_engine_cs *engine,
u32 *reg_state)
{
struct drm_i915_private *dev_priv = engine->i915;
struct i915_perf_stream *stream = dev_priv->perf.oa.exclusive_stream;
if (engine->id != RCS)
return;
@ -2120,7 +2136,8 @@ void i915_oa_init_reg_state(struct intel_engine_cs *engine,
if (!dev_priv->perf.initialized)
return;
gen8_update_reg_state_unlocked(ctx, reg_state);
if (stream)
gen8_update_reg_state_unlocked(ctx, reg_state, stream->oa_config);
}
/**
@ -2643,7 +2660,7 @@ static int read_properties_unlocked(struct drm_i915_private *dev_priv,
struct perf_open_properties *props)
{
u64 __user *uprop = uprops;
int i;
u32 i;
memset(props, 0, sizeof(struct perf_open_properties));
@ -2690,8 +2707,7 @@ static int read_properties_unlocked(struct drm_i915_private *dev_priv,
props->sample_flags |= SAMPLE_OA_REPORT;
break;
case DRM_I915_PERF_PROP_OA_METRICS_SET:
if (value == 0 ||
value > dev_priv->perf.oa.n_builtin_sets) {
if (value == 0) {
DRM_DEBUG("Unknown OA metric set ID\n");
return -EINVAL;
}
@ -2830,6 +2846,8 @@ int i915_perf_open_ioctl(struct drm_device *dev, void *data,
*/
void i915_perf_register(struct drm_i915_private *dev_priv)
{
int ret;
if (!dev_priv->perf.initialized)
return;
@ -2845,44 +2863,40 @@ void i915_perf_register(struct drm_i915_private *dev_priv)
if (!dev_priv->perf.metrics_kobj)
goto exit;
memset(&dev_priv->perf.oa.test_config, 0,
sizeof(dev_priv->perf.oa.test_config));
if (IS_HASWELL(dev_priv)) {
if (i915_perf_register_sysfs_hsw(dev_priv))
goto sysfs_error;
i915_perf_load_test_config_hsw(dev_priv);
} else if (IS_BROADWELL(dev_priv)) {
if (i915_perf_register_sysfs_bdw(dev_priv))
goto sysfs_error;
i915_perf_load_test_config_bdw(dev_priv);
} else if (IS_CHERRYVIEW(dev_priv)) {
if (i915_perf_register_sysfs_chv(dev_priv))
goto sysfs_error;
i915_perf_load_test_config_chv(dev_priv);
} else if (IS_SKYLAKE(dev_priv)) {
if (IS_SKL_GT2(dev_priv)) {
if (i915_perf_register_sysfs_sklgt2(dev_priv))
goto sysfs_error;
} else if (IS_SKL_GT3(dev_priv)) {
if (i915_perf_register_sysfs_sklgt3(dev_priv))
goto sysfs_error;
} else if (IS_SKL_GT4(dev_priv)) {
if (i915_perf_register_sysfs_sklgt4(dev_priv))
goto sysfs_error;
} else
goto sysfs_error;
if (IS_SKL_GT2(dev_priv))
i915_perf_load_test_config_sklgt2(dev_priv);
else if (IS_SKL_GT3(dev_priv))
i915_perf_load_test_config_sklgt3(dev_priv);
else if (IS_SKL_GT4(dev_priv))
i915_perf_load_test_config_sklgt4(dev_priv);
} else if (IS_BROXTON(dev_priv)) {
if (i915_perf_register_sysfs_bxt(dev_priv))
goto sysfs_error;
i915_perf_load_test_config_bxt(dev_priv);
} else if (IS_KABYLAKE(dev_priv)) {
if (IS_KBL_GT2(dev_priv)) {
if (i915_perf_register_sysfs_kblgt2(dev_priv))
goto sysfs_error;
} else if (IS_KBL_GT3(dev_priv)) {
if (i915_perf_register_sysfs_kblgt3(dev_priv))
goto sysfs_error;
} else
goto sysfs_error;
if (IS_KBL_GT2(dev_priv))
i915_perf_load_test_config_kblgt2(dev_priv);
else if (IS_KBL_GT3(dev_priv))
i915_perf_load_test_config_kblgt3(dev_priv);
} else if (IS_GEMINILAKE(dev_priv)) {
if (i915_perf_register_sysfs_glk(dev_priv))
goto sysfs_error;
i915_perf_load_test_config_glk(dev_priv);
}
if (dev_priv->perf.oa.test_config.id == 0)
goto sysfs_error;
ret = sysfs_create_group(dev_priv->perf.metrics_kobj,
&dev_priv->perf.oa.test_config.sysfs_metric);
if (ret)
goto sysfs_error;
goto exit;
sysfs_error:
@ -2907,29 +2921,8 @@ void i915_perf_unregister(struct drm_i915_private *dev_priv)
if (!dev_priv->perf.metrics_kobj)
return;
if (IS_HASWELL(dev_priv))
i915_perf_unregister_sysfs_hsw(dev_priv);
else if (IS_BROADWELL(dev_priv))
i915_perf_unregister_sysfs_bdw(dev_priv);
else if (IS_CHERRYVIEW(dev_priv))
i915_perf_unregister_sysfs_chv(dev_priv);
else if (IS_SKYLAKE(dev_priv)) {
if (IS_SKL_GT2(dev_priv))
i915_perf_unregister_sysfs_sklgt2(dev_priv);
else if (IS_SKL_GT3(dev_priv))
i915_perf_unregister_sysfs_sklgt3(dev_priv);
else if (IS_SKL_GT4(dev_priv))
i915_perf_unregister_sysfs_sklgt4(dev_priv);
} else if (IS_BROXTON(dev_priv))
i915_perf_unregister_sysfs_bxt(dev_priv);
else if (IS_KABYLAKE(dev_priv)) {
if (IS_KBL_GT2(dev_priv))
i915_perf_unregister_sysfs_kblgt2(dev_priv);
else if (IS_KBL_GT3(dev_priv))
i915_perf_unregister_sysfs_kblgt3(dev_priv);
} else if (IS_GEMINILAKE(dev_priv))
i915_perf_unregister_sysfs_glk(dev_priv);
sysfs_remove_group(dev_priv->perf.metrics_kobj,
&dev_priv->perf.oa.test_config.sysfs_metric);
kobject_put(dev_priv->perf.metrics_kobj);
dev_priv->perf.metrics_kobj = NULL;
@ -2988,7 +2981,7 @@ static struct ctl_table dev_root[] = {
*/
void i915_perf_init(struct drm_i915_private *dev_priv)
{
dev_priv->perf.oa.n_builtin_sets = 0;
dev_priv->perf.oa.timestamp_frequency = 0;
if (IS_HASWELL(dev_priv)) {
dev_priv->perf.oa.ops.init_oa_buffer = gen7_init_oa_buffer;
@ -3003,9 +2996,6 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
dev_priv->perf.oa.timestamp_frequency = 12500000;
dev_priv->perf.oa.oa_formats = hsw_oa_formats;
dev_priv->perf.oa.n_builtin_sets =
i915_oa_n_builtin_metric_sets_hsw;
} else if (i915.enable_execlists) {
/* Note: that although we could theoretically also support the
* legacy ringbuffer mode on BDW (and earlier iterations of
@ -3014,6 +3004,16 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
* execlist mode by default.
*/
dev_priv->perf.oa.ops.init_oa_buffer = gen8_init_oa_buffer;
dev_priv->perf.oa.ops.enable_metric_set = gen8_enable_metric_set;
dev_priv->perf.oa.ops.disable_metric_set = gen8_disable_metric_set;
dev_priv->perf.oa.ops.oa_enable = gen8_oa_enable;
dev_priv->perf.oa.ops.oa_disable = gen8_oa_disable;
dev_priv->perf.oa.ops.read = gen8_oa_read;
dev_priv->perf.oa.ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
dev_priv->perf.oa.oa_formats = gen8_plus_oa_formats;
if (IS_GEN8(dev_priv)) {
dev_priv->perf.oa.ctx_oactxctrl_offset = 0x120;
dev_priv->perf.oa.ctx_flexeu0_offset = 0x2ce;
@ -3021,85 +3021,31 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
dev_priv->perf.oa.timestamp_frequency = 12500000;
dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<25);
if (IS_BROADWELL(dev_priv)) {
dev_priv->perf.oa.n_builtin_sets =
i915_oa_n_builtin_metric_sets_bdw;
dev_priv->perf.oa.ops.select_metric_set =
i915_oa_select_metric_set_bdw;
} else if (IS_CHERRYVIEW(dev_priv)) {
dev_priv->perf.oa.n_builtin_sets =
i915_oa_n_builtin_metric_sets_chv;
dev_priv->perf.oa.ops.select_metric_set =
i915_oa_select_metric_set_chv;
}
} else if (IS_GEN9(dev_priv)) {
dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128;
dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de;
dev_priv->perf.oa.timestamp_frequency = 12000000;
dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);
if (IS_SKL_GT2(dev_priv)) {
dev_priv->perf.oa.n_builtin_sets =
i915_oa_n_builtin_metric_sets_sklgt2;
dev_priv->perf.oa.ops.select_metric_set =
i915_oa_select_metric_set_sklgt2;
} else if (IS_SKL_GT3(dev_priv)) {
dev_priv->perf.oa.n_builtin_sets =
i915_oa_n_builtin_metric_sets_sklgt3;
dev_priv->perf.oa.ops.select_metric_set =
i915_oa_select_metric_set_sklgt3;
} else if (IS_SKL_GT4(dev_priv)) {
dev_priv->perf.oa.n_builtin_sets =
i915_oa_n_builtin_metric_sets_sklgt4;
dev_priv->perf.oa.ops.select_metric_set =
i915_oa_select_metric_set_sklgt4;
} else if (IS_BROXTON(dev_priv)) {
dev_priv->perf.oa.timestamp_frequency = 19200000;
dev_priv->perf.oa.n_builtin_sets =
i915_oa_n_builtin_metric_sets_bxt;
dev_priv->perf.oa.ops.select_metric_set =
i915_oa_select_metric_set_bxt;
} else if (IS_KBL_GT2(dev_priv)) {
dev_priv->perf.oa.n_builtin_sets =
i915_oa_n_builtin_metric_sets_kblgt2;
dev_priv->perf.oa.ops.select_metric_set =
i915_oa_select_metric_set_kblgt2;
} else if (IS_KBL_GT3(dev_priv)) {
dev_priv->perf.oa.n_builtin_sets =
i915_oa_n_builtin_metric_sets_kblgt3;
dev_priv->perf.oa.ops.select_metric_set =
i915_oa_select_metric_set_kblgt3;
} else if (IS_GEMINILAKE(dev_priv)) {
switch (dev_priv->info.platform) {
case INTEL_BROXTON:
case INTEL_GEMINILAKE:
dev_priv->perf.oa.timestamp_frequency = 19200000;
dev_priv->perf.oa.n_builtin_sets =
i915_oa_n_builtin_metric_sets_glk;
dev_priv->perf.oa.ops.select_metric_set =
i915_oa_select_metric_set_glk;
}
break;
case INTEL_SKYLAKE:
case INTEL_KABYLAKE:
dev_priv->perf.oa.timestamp_frequency = 12000000;
break;
default:
/* Leave timestamp_frequency to 0 so we can
* detect unsupported platforms.
*/
break;
}
if (dev_priv->perf.oa.n_builtin_sets) {
dev_priv->perf.oa.ops.init_oa_buffer = gen8_init_oa_buffer;
dev_priv->perf.oa.ops.enable_metric_set =
gen8_enable_metric_set;
dev_priv->perf.oa.ops.disable_metric_set =
gen8_disable_metric_set;
dev_priv->perf.oa.ops.oa_enable = gen8_oa_enable;
dev_priv->perf.oa.ops.oa_disable = gen8_oa_disable;
dev_priv->perf.oa.ops.read = gen8_oa_read;
dev_priv->perf.oa.ops.oa_hw_tail_read =
gen8_oa_hw_tail_read;
dev_priv->perf.oa.oa_formats = gen8_plus_oa_formats;
}
}
if (dev_priv->perf.oa.n_builtin_sets) {
if (dev_priv->perf.oa.timestamp_frequency) {
hrtimer_init(&dev_priv->perf.oa.poll_check_timer,
CLOCK_MONOTONIC, HRTIMER_MODE_REL);
dev_priv->perf.oa.poll_check_timer.function = oa_poll_check_timer_cb;

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