This patch adds basic driver implementation for Broadcom's static adc controller used in iProc SoC's family. Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>tirimbino
Raveendra Padasalagi
9 years ago
committed by
Jonathan Cameron
parent
d3c4d0ab3b
commit
4324c97ece
@ -0,0 +1,644 @@ |
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/*
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* Copyright 2016 Broadcom |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License, version 2, as |
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* published by the Free Software Foundation (the "GPL"). |
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* |
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* This program is distributed in the hope that it will be useful, but |
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* WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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* General Public License version 2 (GPLv2) for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* version 2 (GPLv2) along with this source code. |
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*/ |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/io.h> |
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#include <linux/clk.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/regmap.h> |
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#include <linux/delay.h> |
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#include <linux/interrupt.h> |
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#include <linux/platform_device.h> |
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#include <linux/iio/iio.h> |
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/* Below Register's are common to IPROC ADC and Touchscreen IP */ |
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#define IPROC_REGCTL1 0x00 |
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#define IPROC_REGCTL2 0x04 |
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#define IPROC_INTERRUPT_THRES 0x08 |
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#define IPROC_INTERRUPT_MASK 0x0c |
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#define IPROC_INTERRUPT_STATUS 0x10 |
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#define IPROC_ANALOG_CONTROL 0x1c |
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#define IPROC_CONTROLLER_STATUS 0x14 |
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#define IPROC_AUX_DATA 0x20 |
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#define IPROC_SOFT_BYPASS_CONTROL 0x38 |
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#define IPROC_SOFT_BYPASS_DATA 0x3C |
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/* IPROC ADC Channel register offsets */ |
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#define IPROC_ADC_CHANNEL_REGCTL1 0x800 |
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#define IPROC_ADC_CHANNEL_REGCTL2 0x804 |
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#define IPROC_ADC_CHANNEL_STATUS 0x808 |
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#define IPROC_ADC_CHANNEL_INTERRUPT_STATUS 0x80c |
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#define IPROC_ADC_CHANNEL_INTERRUPT_MASK 0x810 |
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#define IPROC_ADC_CHANNEL_DATA 0x814 |
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#define IPROC_ADC_CHANNEL_OFFSET 0x20 |
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/* Bit definitions for IPROC_REGCTL2 */ |
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#define IPROC_ADC_AUXIN_SCAN_ENA BIT(0) |
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#define IPROC_ADC_PWR_LDO BIT(5) |
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#define IPROC_ADC_PWR_ADC BIT(4) |
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#define IPROC_ADC_PWR_BG BIT(3) |
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#define IPROC_ADC_CONTROLLER_EN BIT(17) |
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/* Bit definitions for IPROC_INTERRUPT_MASK and IPROC_INTERRUPT_STATUS */ |
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#define IPROC_ADC_AUXDATA_RDY_INTR BIT(3) |
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#define IPROC_ADC_INTR 9 |
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#define IPROC_ADC_INTR_MASK (0xFF << IPROC_ADC_INTR) |
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/* Bit definitions for IPROC_ANALOG_CONTROL */ |
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#define IPROC_ADC_CHANNEL_SEL 11 |
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#define IPROC_ADC_CHANNEL_SEL_MASK (0x7 << IPROC_ADC_CHANNEL_SEL) |
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/* Bit definitions for IPROC_ADC_CHANNEL_REGCTL1 */ |
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#define IPROC_ADC_CHANNEL_ROUNDS 0x2 |
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#define IPROC_ADC_CHANNEL_ROUNDS_MASK (0x3F << IPROC_ADC_CHANNEL_ROUNDS) |
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#define IPROC_ADC_CHANNEL_MODE 0x1 |
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#define IPROC_ADC_CHANNEL_MODE_MASK (0x1 << IPROC_ADC_CHANNEL_MODE) |
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#define IPROC_ADC_CHANNEL_MODE_TDM 0x1 |
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#define IPROC_ADC_CHANNEL_MODE_SNAPSHOT 0x0 |
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#define IPROC_ADC_CHANNEL_ENABLE 0x0 |
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#define IPROC_ADC_CHANNEL_ENABLE_MASK 0x1 |
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/* Bit definitions for IPROC_ADC_CHANNEL_REGCTL2 */ |
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#define IPROC_ADC_CHANNEL_WATERMARK 0x0 |
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#define IPROC_ADC_CHANNEL_WATERMARK_MASK \ |
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(0x3F << IPROC_ADC_CHANNEL_WATERMARK) |
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#define IPROC_ADC_WATER_MARK_LEVEL 0x1 |
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/* Bit definitions for IPROC_ADC_CHANNEL_STATUS */ |
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#define IPROC_ADC_CHANNEL_DATA_LOST 0x0 |
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#define IPROC_ADC_CHANNEL_DATA_LOST_MASK \ |
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(0x0 << IPROC_ADC_CHANNEL_DATA_LOST) |
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#define IPROC_ADC_CHANNEL_VALID_ENTERIES 0x1 |
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#define IPROC_ADC_CHANNEL_VALID_ENTERIES_MASK \ |
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(0xFF << IPROC_ADC_CHANNEL_VALID_ENTERIES) |
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#define IPROC_ADC_CHANNEL_TOTAL_ENTERIES 0x9 |
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#define IPROC_ADC_CHANNEL_TOTAL_ENTERIES_MASK \ |
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(0xFF << IPROC_ADC_CHANNEL_TOTAL_ENTERIES) |
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/* Bit definitions for IPROC_ADC_CHANNEL_INTERRUPT_MASK */ |
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#define IPROC_ADC_CHANNEL_WTRMRK_INTR 0x0 |
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#define IPROC_ADC_CHANNEL_WTRMRK_INTR_MASK \ |
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(0x1 << IPROC_ADC_CHANNEL_WTRMRK_INTR) |
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#define IPROC_ADC_CHANNEL_FULL_INTR 0x1 |
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#define IPROC_ADC_CHANNEL_FULL_INTR_MASK \ |
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(0x1 << IPROC_ADC_IPROC_ADC_CHANNEL_FULL_INTR) |
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#define IPROC_ADC_CHANNEL_EMPTY_INTR 0x2 |
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#define IPROC_ADC_CHANNEL_EMPTY_INTR_MASK \ |
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(0x1 << IPROC_ADC_CHANNEL_EMPTY_INTR) |
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#define IPROC_ADC_WATER_MARK_INTR_ENABLE 0x1 |
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/* Number of time to retry a set of the interrupt mask reg */ |
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#define IPROC_ADC_INTMASK_RETRY_ATTEMPTS 10 |
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#define IPROC_ADC_READ_TIMEOUT (HZ*2) |
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#define iproc_adc_dbg_reg(dev, priv, reg) \ |
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do { \
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u32 val; \
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regmap_read(priv->regmap, reg, &val); \
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dev_dbg(dev, "%20s= 0x%08x\n", #reg, val); \
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} while (0) |
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struct iproc_adc_priv { |
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struct regmap *regmap; |
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struct clk *adc_clk; |
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struct mutex mutex; |
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int irqno; |
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int chan_val; |
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int chan_id; |
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struct completion completion; |
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}; |
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static void iproc_adc_reg_dump(struct iio_dev *indio_dev) |
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{ |
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struct device *dev = &indio_dev->dev; |
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struct iproc_adc_priv *adc_priv = iio_priv(indio_dev); |
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iproc_adc_dbg_reg(dev, adc_priv, IPROC_REGCTL1); |
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iproc_adc_dbg_reg(dev, adc_priv, IPROC_REGCTL2); |
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iproc_adc_dbg_reg(dev, adc_priv, IPROC_INTERRUPT_THRES); |
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iproc_adc_dbg_reg(dev, adc_priv, IPROC_INTERRUPT_MASK); |
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iproc_adc_dbg_reg(dev, adc_priv, IPROC_INTERRUPT_STATUS); |
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iproc_adc_dbg_reg(dev, adc_priv, IPROC_CONTROLLER_STATUS); |
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iproc_adc_dbg_reg(dev, adc_priv, IPROC_ANALOG_CONTROL); |
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iproc_adc_dbg_reg(dev, adc_priv, IPROC_AUX_DATA); |
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iproc_adc_dbg_reg(dev, adc_priv, IPROC_SOFT_BYPASS_CONTROL); |
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iproc_adc_dbg_reg(dev, adc_priv, IPROC_SOFT_BYPASS_DATA); |
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} |
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static irqreturn_t iproc_adc_interrupt_handler(int irq, void *data) |
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{ |
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u32 channel_intr_status; |
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u32 intr_status; |
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u32 intr_mask; |
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struct iio_dev *indio_dev = data; |
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struct iproc_adc_priv *adc_priv = iio_priv(indio_dev); |
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/*
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* This interrupt is shared with the touchscreen driver. |
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* Make sure this interrupt is intended for us. |
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* Handle only ADC channel specific interrupts. |
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*/ |
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regmap_read(adc_priv->regmap, IPROC_INTERRUPT_STATUS, &intr_status); |
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regmap_read(adc_priv->regmap, IPROC_INTERRUPT_MASK, &intr_mask); |
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intr_status = intr_status & intr_mask; |
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channel_intr_status = (intr_status & IPROC_ADC_INTR_MASK) >> |
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IPROC_ADC_INTR; |
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if (channel_intr_status) |
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return IRQ_WAKE_THREAD; |
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return IRQ_NONE; |
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} |
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static irqreturn_t iproc_adc_interrupt_thread(int irq, void *data) |
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{ |
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irqreturn_t retval = IRQ_NONE; |
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struct iproc_adc_priv *adc_priv; |
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struct iio_dev *indio_dev = data; |
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unsigned int valid_entries; |
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u32 intr_status; |
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u32 intr_channels; |
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u32 channel_status; |
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u32 ch_intr_status; |
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adc_priv = iio_priv(indio_dev); |
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regmap_read(adc_priv->regmap, IPROC_INTERRUPT_STATUS, &intr_status); |
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dev_dbg(&indio_dev->dev, "iproc_adc_interrupt_thread(),INTRPT_STS:%x\n", |
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intr_status); |
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intr_channels = (intr_status & IPROC_ADC_INTR_MASK) >> IPROC_ADC_INTR; |
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if (intr_channels) { |
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regmap_read(adc_priv->regmap, |
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IPROC_ADC_CHANNEL_INTERRUPT_STATUS + |
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IPROC_ADC_CHANNEL_OFFSET * adc_priv->chan_id, |
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&ch_intr_status); |
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if (ch_intr_status & IPROC_ADC_CHANNEL_WTRMRK_INTR_MASK) { |
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regmap_read(adc_priv->regmap, |
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IPROC_ADC_CHANNEL_STATUS + |
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IPROC_ADC_CHANNEL_OFFSET * |
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adc_priv->chan_id, |
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&channel_status); |
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valid_entries = ((channel_status & |
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IPROC_ADC_CHANNEL_VALID_ENTERIES_MASK) >> |
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IPROC_ADC_CHANNEL_VALID_ENTERIES); |
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if (valid_entries >= 1) { |
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regmap_read(adc_priv->regmap, |
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IPROC_ADC_CHANNEL_DATA + |
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IPROC_ADC_CHANNEL_OFFSET * |
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adc_priv->chan_id, |
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&adc_priv->chan_val); |
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complete(&adc_priv->completion); |
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} else { |
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dev_err(&indio_dev->dev, |
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"No data rcvd on channel %d\n", |
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adc_priv->chan_id); |
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} |
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regmap_write(adc_priv->regmap, |
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IPROC_ADC_CHANNEL_INTERRUPT_MASK + |
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IPROC_ADC_CHANNEL_OFFSET * |
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adc_priv->chan_id, |
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(ch_intr_status & |
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~(IPROC_ADC_CHANNEL_WTRMRK_INTR_MASK))); |
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} |
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regmap_write(adc_priv->regmap, |
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IPROC_ADC_CHANNEL_INTERRUPT_STATUS + |
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IPROC_ADC_CHANNEL_OFFSET * adc_priv->chan_id, |
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ch_intr_status); |
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regmap_write(adc_priv->regmap, IPROC_INTERRUPT_STATUS, |
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intr_channels); |
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retval = IRQ_HANDLED; |
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} |
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return retval; |
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} |
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static int iproc_adc_do_read(struct iio_dev *indio_dev, |
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int channel, |
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u16 *p_adc_data) |
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{ |
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int read_len = 0; |
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u32 val; |
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u32 mask; |
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u32 val_check; |
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int failed_cnt = 0; |
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struct iproc_adc_priv *adc_priv = iio_priv(indio_dev); |
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mutex_lock(&adc_priv->mutex); |
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/*
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* After a read is complete the ADC interrupts will be disabled so |
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* we can assume this section of code is safe from interrupts. |
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*/ |
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adc_priv->chan_val = -1; |
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adc_priv->chan_id = channel; |
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reinit_completion(&adc_priv->completion); |
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/* Clear any pending interrupt */ |
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regmap_update_bits(adc_priv->regmap, IPROC_INTERRUPT_STATUS, |
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IPROC_ADC_INTR_MASK | IPROC_ADC_AUXDATA_RDY_INTR, |
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((0x0 << channel) << IPROC_ADC_INTR) | |
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IPROC_ADC_AUXDATA_RDY_INTR); |
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/* Configure channel for snapshot mode and enable */ |
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val = (BIT(IPROC_ADC_CHANNEL_ROUNDS) | |
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(IPROC_ADC_CHANNEL_MODE_SNAPSHOT << IPROC_ADC_CHANNEL_MODE) | |
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(0x1 << IPROC_ADC_CHANNEL_ENABLE)); |
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mask = IPROC_ADC_CHANNEL_ROUNDS_MASK | IPROC_ADC_CHANNEL_MODE_MASK | |
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IPROC_ADC_CHANNEL_ENABLE_MASK; |
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regmap_update_bits(adc_priv->regmap, (IPROC_ADC_CHANNEL_REGCTL1 + |
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IPROC_ADC_CHANNEL_OFFSET * channel), |
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mask, val); |
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/* Set the Watermark for a channel */ |
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regmap_update_bits(adc_priv->regmap, (IPROC_ADC_CHANNEL_REGCTL2 + |
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IPROC_ADC_CHANNEL_OFFSET * channel), |
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IPROC_ADC_CHANNEL_WATERMARK_MASK, |
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0x1); |
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/* Enable water mark interrupt */ |
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regmap_update_bits(adc_priv->regmap, (IPROC_ADC_CHANNEL_INTERRUPT_MASK + |
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IPROC_ADC_CHANNEL_OFFSET * |
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channel), |
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IPROC_ADC_CHANNEL_WTRMRK_INTR_MASK, |
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IPROC_ADC_WATER_MARK_INTR_ENABLE); |
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regmap_read(adc_priv->regmap, IPROC_INTERRUPT_MASK, &val); |
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/* Enable ADC interrupt for a channel */ |
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val |= (BIT(channel) << IPROC_ADC_INTR); |
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regmap_write(adc_priv->regmap, IPROC_INTERRUPT_MASK, val); |
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/*
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* There seems to be a very rare issue where writing to this register |
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* does not take effect. To work around the issue we will try multiple |
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* writes. In total we will spend about 10*10 = 100 us attempting this. |
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* Testing has shown that this may loop a few time, but we have never |
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* hit the full count. |
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*/ |
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regmap_read(adc_priv->regmap, IPROC_INTERRUPT_MASK, &val_check); |
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while (val_check != val) { |
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failed_cnt++; |
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if (failed_cnt > IPROC_ADC_INTMASK_RETRY_ATTEMPTS) |
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break; |
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udelay(10); |
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regmap_update_bits(adc_priv->regmap, IPROC_INTERRUPT_MASK, |
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IPROC_ADC_INTR_MASK, |
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((0x1 << channel) << |
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IPROC_ADC_INTR)); |
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regmap_read(adc_priv->regmap, IPROC_INTERRUPT_MASK, &val_check); |
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} |
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if (failed_cnt) { |
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dev_dbg(&indio_dev->dev, |
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"IntMask failed (%d times)", failed_cnt); |
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if (failed_cnt > IPROC_ADC_INTMASK_RETRY_ATTEMPTS) { |
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dev_err(&indio_dev->dev, |
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"IntMask set failed. Read will likely fail."); |
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read_len = -EIO; |
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goto adc_err; |
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}; |
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} |
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regmap_read(adc_priv->regmap, IPROC_INTERRUPT_MASK, &val_check); |
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if (wait_for_completion_timeout(&adc_priv->completion, |
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IPROC_ADC_READ_TIMEOUT) > 0) { |
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/* Only the lower 16 bits are relevant */ |
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*p_adc_data = adc_priv->chan_val & 0xFFFF; |
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read_len = sizeof(*p_adc_data); |
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} else { |
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/*
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* We never got the interrupt, something went wrong. |
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* Perhaps the interrupt may still be coming, we do not want |
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* that now. Lets disable the ADC interrupt, and clear the |
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* status to put it back in to normal state. |
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*/ |
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read_len = -ETIMEDOUT; |
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goto adc_err; |
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} |
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mutex_unlock(&adc_priv->mutex); |
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return read_len; |
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adc_err: |
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regmap_update_bits(adc_priv->regmap, IPROC_INTERRUPT_MASK, |
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IPROC_ADC_INTR_MASK, |
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((0x0 << channel) << IPROC_ADC_INTR)); |
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regmap_update_bits(adc_priv->regmap, IPROC_INTERRUPT_STATUS, |
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IPROC_ADC_INTR_MASK, |
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((0x0 << channel) << IPROC_ADC_INTR)); |
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dev_err(&indio_dev->dev, "Timed out waiting for ADC data!\n"); |
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iproc_adc_reg_dump(indio_dev); |
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mutex_unlock(&adc_priv->mutex); |
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return read_len; |
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} |
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static int iproc_adc_enable(struct iio_dev *indio_dev) |
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{ |
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u32 val; |
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u32 channel_id; |
||||||
|
struct iproc_adc_priv *adc_priv = iio_priv(indio_dev); |
||||||
|
int ret; |
||||||
|
|
||||||
|
/* Set i_amux = 3b'000, select channel 0 */ |
||||||
|
ret = regmap_update_bits(adc_priv->regmap, IPROC_ANALOG_CONTROL, |
||||||
|
IPROC_ADC_CHANNEL_SEL_MASK, 0); |
||||||
|
if (ret) { |
||||||
|
dev_err(&indio_dev->dev, |
||||||
|
"failed to write IPROC_ANALOG_CONTROL %d\n", ret); |
||||||
|
return ret; |
||||||
|
} |
||||||
|
adc_priv->chan_val = -1; |
||||||
|
|
||||||
|
/*
|
||||||
|
* PWR up LDO, ADC, and Band Gap (0 to enable) |
||||||
|
* Also enable ADC controller (set high) |
||||||
|
*/ |
||||||
|
ret = regmap_read(adc_priv->regmap, IPROC_REGCTL2, &val); |
||||||
|
if (ret) { |
||||||
|
dev_err(&indio_dev->dev, |
||||||
|
"failed to read IPROC_REGCTL2 %d\n", ret); |
||||||
|
return ret; |
||||||
|
} |
||||||
|
|
||||||
|
val &= ~(IPROC_ADC_PWR_LDO | IPROC_ADC_PWR_ADC | IPROC_ADC_PWR_BG); |
||||||
|
|
||||||
|
ret = regmap_write(adc_priv->regmap, IPROC_REGCTL2, val); |
||||||
|
if (ret) { |
||||||
|
dev_err(&indio_dev->dev, |
||||||
|
"failed to write IPROC_REGCTL2 %d\n", ret); |
||||||
|
return ret; |
||||||
|
} |
||||||
|
|
||||||
|
ret = regmap_read(adc_priv->regmap, IPROC_REGCTL2, &val); |
||||||
|
if (ret) { |
||||||
|
dev_err(&indio_dev->dev, |
||||||
|
"failed to read IPROC_REGCTL2 %d\n", ret); |
||||||
|
return ret; |
||||||
|
} |
||||||
|
|
||||||
|
val |= IPROC_ADC_CONTROLLER_EN; |
||||||
|
ret = regmap_write(adc_priv->regmap, IPROC_REGCTL2, val); |
||||||
|
if (ret) { |
||||||
|
dev_err(&indio_dev->dev, |
||||||
|
"failed to write IPROC_REGCTL2 %d\n", ret); |
||||||
|
return ret; |
||||||
|
} |
||||||
|
|
||||||
|
for (channel_id = 0; channel_id < indio_dev->num_channels; |
||||||
|
channel_id++) { |
||||||
|
ret = regmap_write(adc_priv->regmap, |
||||||
|
IPROC_ADC_CHANNEL_INTERRUPT_MASK + |
||||||
|
IPROC_ADC_CHANNEL_OFFSET * channel_id, 0); |
||||||
|
if (ret) { |
||||||
|
dev_err(&indio_dev->dev, |
||||||
|
"failed to write ADC_CHANNEL_INTERRUPT_MASK %d\n", |
||||||
|
ret); |
||||||
|
return ret; |
||||||
|
} |
||||||
|
|
||||||
|
ret = regmap_write(adc_priv->regmap, |
||||||
|
IPROC_ADC_CHANNEL_INTERRUPT_STATUS + |
||||||
|
IPROC_ADC_CHANNEL_OFFSET * channel_id, 0); |
||||||
|
if (ret) { |
||||||
|
dev_err(&indio_dev->dev, |
||||||
|
"failed to write ADC_CHANNEL_INTERRUPT_STATUS %d\n", |
||||||
|
ret); |
||||||
|
return ret; |
||||||
|
} |
||||||
|
} |
||||||
|
|
||||||
|
return 0; |
||||||
|
} |
||||||
|
|
||||||
|
static void iproc_adc_disable(struct iio_dev *indio_dev) |
||||||
|
{ |
||||||
|
u32 val; |
||||||
|
int ret; |
||||||
|
struct iproc_adc_priv *adc_priv = iio_priv(indio_dev); |
||||||
|
|
||||||
|
ret = regmap_read(adc_priv->regmap, IPROC_REGCTL2, &val); |
||||||
|
if (ret) { |
||||||
|
dev_err(&indio_dev->dev, |
||||||
|
"failed to read IPROC_REGCTL2 %d\n", ret); |
||||||
|
return; |
||||||
|
} |
||||||
|
|
||||||
|
val &= ~IPROC_ADC_CONTROLLER_EN; |
||||||
|
ret = regmap_write(adc_priv->regmap, IPROC_REGCTL2, val); |
||||||
|
if (ret) { |
||||||
|
dev_err(&indio_dev->dev, |
||||||
|
"failed to write IPROC_REGCTL2 %d\n", ret); |
||||||
|
return; |
||||||
|
} |
||||||
|
} |
||||||
|
|
||||||
|
static int iproc_adc_read_raw(struct iio_dev *indio_dev, |
||||||
|
struct iio_chan_spec const *chan, |
||||||
|
int *val, |
||||||
|
int *val2, |
||||||
|
long mask) |
||||||
|
{ |
||||||
|
u16 adc_data; |
||||||
|
int err; |
||||||
|
|
||||||
|
switch (mask) { |
||||||
|
case IIO_CHAN_INFO_RAW: |
||||||
|
err = iproc_adc_do_read(indio_dev, chan->channel, &adc_data); |
||||||
|
if (err < 0) |
||||||
|
return err; |
||||||
|
*val = adc_data; |
||||||
|
return IIO_VAL_INT; |
||||||
|
case IIO_CHAN_INFO_SCALE: |
||||||
|
switch (chan->type) { |
||||||
|
case IIO_VOLTAGE: |
||||||
|
*val = 1800; |
||||||
|
*val2 = 10; |
||||||
|
return IIO_VAL_FRACTIONAL_LOG2; |
||||||
|
default: |
||||||
|
return -EINVAL; |
||||||
|
} |
||||||
|
default: |
||||||
|
return -EINVAL; |
||||||
|
} |
||||||
|
} |
||||||
|
|
||||||
|
static const struct iio_info iproc_adc_iio_info = { |
||||||
|
.read_raw = &iproc_adc_read_raw, |
||||||
|
.driver_module = THIS_MODULE, |
||||||
|
}; |
||||||
|
|
||||||
|
#define IPROC_ADC_CHANNEL(_index, _id) { \ |
||||||
|
.type = IIO_VOLTAGE, \
|
||||||
|
.indexed = 1, \
|
||||||
|
.channel = _index, \
|
||||||
|
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
|
||||||
|
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
|
||||||
|
.datasheet_name = _id, \
|
||||||
|
} |
||||||
|
|
||||||
|
static const struct iio_chan_spec iproc_adc_iio_channels[] = { |
||||||
|
IPROC_ADC_CHANNEL(0, "adc0"), |
||||||
|
IPROC_ADC_CHANNEL(1, "adc1"), |
||||||
|
IPROC_ADC_CHANNEL(2, "adc2"), |
||||||
|
IPROC_ADC_CHANNEL(3, "adc3"), |
||||||
|
IPROC_ADC_CHANNEL(4, "adc4"), |
||||||
|
IPROC_ADC_CHANNEL(5, "adc5"), |
||||||
|
IPROC_ADC_CHANNEL(6, "adc6"), |
||||||
|
IPROC_ADC_CHANNEL(7, "adc7"), |
||||||
|
}; |
||||||
|
|
||||||
|
static int iproc_adc_probe(struct platform_device *pdev) |
||||||
|
{ |
||||||
|
struct iproc_adc_priv *adc_priv; |
||||||
|
struct iio_dev *indio_dev = NULL; |
||||||
|
int ret; |
||||||
|
|
||||||
|
indio_dev = devm_iio_device_alloc(&pdev->dev, |
||||||
|
sizeof(*adc_priv)); |
||||||
|
if (!indio_dev) { |
||||||
|
dev_err(&pdev->dev, "failed to allocate iio device\n"); |
||||||
|
return -ENOMEM; |
||||||
|
} |
||||||
|
|
||||||
|
adc_priv = iio_priv(indio_dev); |
||||||
|
platform_set_drvdata(pdev, indio_dev); |
||||||
|
|
||||||
|
mutex_init(&adc_priv->mutex); |
||||||
|
|
||||||
|
init_completion(&adc_priv->completion); |
||||||
|
|
||||||
|
adc_priv->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, |
||||||
|
"adc-syscon"); |
||||||
|
if (IS_ERR(adc_priv->regmap)) { |
||||||
|
dev_err(&pdev->dev, "failed to get handle for tsc syscon\n"); |
||||||
|
ret = PTR_ERR(adc_priv->regmap); |
||||||
|
return ret; |
||||||
|
} |
||||||
|
|
||||||
|
adc_priv->adc_clk = devm_clk_get(&pdev->dev, "tsc_clk"); |
||||||
|
if (IS_ERR(adc_priv->adc_clk)) { |
||||||
|
dev_err(&pdev->dev, |
||||||
|
"failed getting clock tsc_clk\n"); |
||||||
|
ret = PTR_ERR(adc_priv->adc_clk); |
||||||
|
return ret; |
||||||
|
} |
||||||
|
|
||||||
|
adc_priv->irqno = platform_get_irq(pdev, 0); |
||||||
|
if (adc_priv->irqno <= 0) { |
||||||
|
dev_err(&pdev->dev, "platform_get_irq failed\n"); |
||||||
|
ret = -ENODEV; |
||||||
|
return ret; |
||||||
|
} |
||||||
|
|
||||||
|
ret = regmap_update_bits(adc_priv->regmap, IPROC_REGCTL2, |
||||||
|
IPROC_ADC_AUXIN_SCAN_ENA, 0); |
||||||
|
if (ret) { |
||||||
|
dev_err(&pdev->dev, "failed to write IPROC_REGCTL2 %d\n", ret); |
||||||
|
return ret; |
||||||
|
} |
||||||
|
|
||||||
|
ret = devm_request_threaded_irq(&pdev->dev, adc_priv->irqno, |
||||||
|
iproc_adc_interrupt_thread, |
||||||
|
iproc_adc_interrupt_handler, |
||||||
|
IRQF_SHARED, "iproc-adc", indio_dev); |
||||||
|
if (ret) { |
||||||
|
dev_err(&pdev->dev, "request_irq error %d\n", ret); |
||||||
|
return ret; |
||||||
|
} |
||||||
|
|
||||||
|
ret = clk_prepare_enable(adc_priv->adc_clk); |
||||||
|
if (ret) { |
||||||
|
dev_err(&pdev->dev, |
||||||
|
"clk_prepare_enable failed %d\n", ret); |
||||||
|
return ret; |
||||||
|
} |
||||||
|
|
||||||
|
ret = iproc_adc_enable(indio_dev); |
||||||
|
if (ret) { |
||||||
|
dev_err(&pdev->dev, "failed to enable adc %d\n", ret); |
||||||
|
goto err_adc_enable; |
||||||
|
} |
||||||
|
|
||||||
|
indio_dev->name = "iproc-static-adc"; |
||||||
|
indio_dev->dev.parent = &pdev->dev; |
||||||
|
indio_dev->dev.of_node = pdev->dev.of_node; |
||||||
|
indio_dev->info = &iproc_adc_iio_info; |
||||||
|
indio_dev->modes = INDIO_DIRECT_MODE; |
||||||
|
indio_dev->channels = iproc_adc_iio_channels; |
||||||
|
indio_dev->num_channels = ARRAY_SIZE(iproc_adc_iio_channels); |
||||||
|
|
||||||
|
ret = iio_device_register(indio_dev); |
||||||
|
if (ret) { |
||||||
|
dev_err(&pdev->dev, "iio_device_register failed:err %d\n", ret); |
||||||
|
goto err_clk; |
||||||
|
} |
||||||
|
|
||||||
|
return 0; |
||||||
|
|
||||||
|
err_clk: |
||||||
|
iproc_adc_disable(indio_dev); |
||||||
|
err_adc_enable: |
||||||
|
clk_disable_unprepare(adc_priv->adc_clk); |
||||||
|
|
||||||
|
return ret; |
||||||
|
} |
||||||
|
|
||||||
|
static int iproc_adc_remove(struct platform_device *pdev) |
||||||
|
{ |
||||||
|
struct iio_dev *indio_dev = platform_get_drvdata(pdev); |
||||||
|
struct iproc_adc_priv *adc_priv = iio_priv(indio_dev); |
||||||
|
|
||||||
|
iio_device_unregister(indio_dev); |
||||||
|
iproc_adc_disable(indio_dev); |
||||||
|
clk_disable_unprepare(adc_priv->adc_clk); |
||||||
|
|
||||||
|
return 0; |
||||||
|
} |
||||||
|
|
||||||
|
static const struct of_device_id iproc_adc_of_match[] = { |
||||||
|
{.compatible = "brcm,iproc-static-adc", }, |
||||||
|
{ }, |
||||||
|
}; |
||||||
|
MODULE_DEVICE_TABLE(of, iproc_adc_of_match); |
||||||
|
|
||||||
|
static struct platform_driver iproc_adc_driver = { |
||||||
|
.probe = iproc_adc_probe, |
||||||
|
.remove = iproc_adc_remove, |
||||||
|
.driver = { |
||||||
|
.name = "iproc-static-adc", |
||||||
|
.of_match_table = of_match_ptr(iproc_adc_of_match), |
||||||
|
}, |
||||||
|
}; |
||||||
|
module_platform_driver(iproc_adc_driver); |
||||||
|
|
||||||
|
MODULE_DESCRIPTION("Broadcom iProc ADC controller driver"); |
||||||
|
MODULE_AUTHOR("Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>"); |
||||||
|
MODULE_LICENSE("GPL v2"); |
||||||
Loading…
Reference in new issue