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ARM: dts: msm: add support of DP PCLK bond mode for SA8195p

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Add DP PCLK bond mode options.
Add the shared bonding pclk parent.

Change-Id: Ifecd71218ae35b976e75271529c883fac8c06596
Signed-off-by: Jim Wang <jimwan@codeaurora.org>
tirimbino
Jim Wang 5 years ago committed by Gerrit - the friendly Code Review server
parent 6e0829cb46
commit 02efcc8c33
1 changed files with 14 additions and 6 deletions
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  1. 20
      arch/arm64/boot/dts/qcom/sdmshrike-sde.dtsi

20
arch/arm64/boot/dts/qcom/sdmshrike-sde.dtsi
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@ -618,6 +618,7 @@
qcom,phy-index = <0>;
qcom,bond-dual-ctrl = <1 0>;
qcom,bond-tri-ctrl = <2 0 1>;
reg = <0xae90000 0x0dc>,
<0xae90200 0x0c0>,
@ -653,13 +654,15 @@
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>,
<&mdss_dp0_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>,
<&mdss_dp2_pll DP_VCO_DIVIDED_CLK_SRC_MUX>;
clock-names = "core_aux_clk", "core_usb_ref_clk_src",
"core_usb_ref_clk", "core_usb_pipe_clk",
"link_clk", "link_iface_clk",
"crypto_clk", "pixel_clk_rcg", "pixel_parent",
"pixel1_clk_rcg", "pixel1_parent",
"strm0_pixel_clk", "strm1_pixel_clk";
"strm0_pixel_clk", "strm1_pixel_clk",
"bond_pixel_parent";
qcom,phy-version = <0x420>;
qcom,phy-mode = "dp";
@ -766,13 +769,15 @@
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>,
<&mdss_dp1_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>,
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>,
<&mdss_dp2_pll DP_VCO_DIVIDED_CLK_SRC_MUX>;
clock-names = "core_aux_clk", "core_usb_ref_clk_src",
"core_usb_ref_clk", "core_usb_pipe_clk",
"link_clk", "link_iface_clk",
"crypto_clk", "pixel_clk_rcg", "pixel_parent",
"pixel1_clk_rcg", "pixel1_parent",
"strm0_pixel_clk", "strm1_pixel_clk";
"strm0_pixel_clk", "strm1_pixel_clk",
"bond_pixel_parent";
qcom,phy-version = <0x420>;
qcom,phy-mode = "dp";
@ -872,11 +877,13 @@
<&clock_dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
<&clock_dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>,
<&mdss_edp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,
<&clock_dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
<&clock_dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>,
<&mdss_dp2_pll DP_VCO_DIVIDED_CLK_SRC_MUX>;
clock-names = "core_aux_clk", "core_ref_clk",
"link_clk", "link_iface_clk",
"pixel_clk_rcg", "pixel_parent",
"strm0_pixel_clk";
"strm0_pixel_clk",
"bond_pixel_parent";
qcom,phy-version = <0x500>;
qcom,phy-mode = "edp";
@ -895,6 +902,7 @@
qcom,dsc-feature-enable;
qcom,fec-feature-enable;
qcom,widebus-enable;
qcom,max-dp-dsc-blks = <2>;
qcom,max-dp-dsc-input-width-pixs = <2048>;

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