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297 lines
8.8 KiB
297 lines
8.8 KiB
/*
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* arch/mips/ddb5476/setup.c -- NEC DDB Vrc-5476 setup routines
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*
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* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
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* Sony Software Development Center Europe (SDCE), Brussels
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*/
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#include <linux/init.h>
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#include <linux/kbd_ll.h>
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#include <linux/kernel.h>
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#include <linux/kdev_t.h>
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#include <linux/types.h>
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <asm/addrspace.h>
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#include <asm/bcache.h>
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#include <asm/irq.h>
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#include <asm/reboot.h>
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#include <asm/gdb-stub.h>
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#include <asm/time.h>
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#include <asm/debug.h>
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#include <asm/traps.h>
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#include <asm/ddb5xxx/ddb5xxx.h>
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// #define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */
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#ifdef USE_CPU_COUNTER_TIMER
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#define CPU_COUNTER_FREQUENCY 83000000
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#else
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/* otherwise we use general purpose timer */
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#define TIMER_FREQUENCY 83000000
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#define TIMER_BASE DDB_T2CTRL
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#define TIMER_IRQ (VRC5476_IRQ_BASE + VRC5476_IRQ_GPT)
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#endif
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static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
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static void ddb_machine_restart(char *command)
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{
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u32 t;
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/* PCI cold reset */
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t = ddb_in32(DDB_PCICTRL + 4);
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t |= 0x40000000;
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ddb_out32(DDB_PCICTRL + 4, t);
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/* CPU cold reset */
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t = ddb_in32(DDB_CPUSTAT);
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t |= 1;
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ddb_out32(DDB_CPUSTAT, t);
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/* Call the PROM */
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back_to_prom();
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}
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static void ddb_machine_halt(void)
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{
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printk(KERN_NOTICE "DDB Vrc-5476 halted.\n");
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while (1);
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}
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static void ddb_machine_power_off(void)
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{
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printk(KERN_NOTICE "DDB Vrc-5476 halted. Please turn off the power.\n");
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while (1);
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}
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extern void rtc_ds1386_init(unsigned long base);
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static void __init ddb_time_init(void)
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{
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#if defined(USE_CPU_COUNTER_TIMER)
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mips_hpt_frequency = CPU_COUNTER_FREQUENCY;
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#endif
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/* we have ds1396 RTC chip */
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rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE));
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}
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extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
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static void __init ddb_timer_setup(struct irqaction *irq)
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{
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#if defined(USE_CPU_COUNTER_TIMER)
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unsigned int count;
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/* we are using the cpu counter for timer interrupts */
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setup_irq(CPU_IRQ_BASE + 7, irq);
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/* to generate the first timer interrupt */
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count = read_c0_count();
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write_c0_compare(count + 1000);
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#else
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ddb_out32(TIMER_BASE, TIMER_FREQUENCY/HZ);
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ddb_out32(TIMER_BASE+4, 0x1); /* enable timer */
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setup_irq(TIMER_IRQ, irq);
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#endif
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}
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static struct {
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struct resource dma1;
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struct resource timer;
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struct resource rtc;
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struct resource dma_page_reg;
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struct resource dma2;
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} ddb5476_ioport = {
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{
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"dma1", 0x00, 0x1f, IORESOURCE_BUSY}, {
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"timer", 0x40, 0x5f, IORESOURCE_BUSY}, {
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"rtc", 0x70, 0x7f, IORESOURCE_BUSY}, {
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"dma page reg", 0x80, 0x8f, IORESOURCE_BUSY}, {
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"dma2", 0xc0, 0xdf, IORESOURCE_BUSY}
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};
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static struct {
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struct resource nile4;
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} ddb5476_iomem = {
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{ "Nile 4", DDB_BASE, DDB_BASE + DDB_SIZE - 1, IORESOURCE_BUSY}
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};
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static void ddb5476_board_init(void);
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static void __init ddb5476_setup(void)
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{
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set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
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board_time_init = ddb_time_init;
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board_timer_setup = ddb_timer_setup;
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_machine_restart = ddb_machine_restart;
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_machine_halt = ddb_machine_halt;
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_machine_power_off = ddb_machine_power_off;
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/* request io port/mem resources */
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if (request_resource(&ioport_resource, &ddb5476_ioport.dma1) ||
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request_resource(&ioport_resource, &ddb5476_ioport.timer) ||
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request_resource(&ioport_resource, &ddb5476_ioport.rtc) ||
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request_resource(&ioport_resource,
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&ddb5476_ioport.dma_page_reg)
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|| request_resource(&ioport_resource, &ddb5476_ioport.dma2)
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|| request_resource(&iomem_resource, &ddb5476_iomem.nile4)) {
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printk
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("ddb_setup - requesting oo port resources failed.\n");
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for (;;);
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}
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/* Reboot on panic */
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panic_timeout = 180;
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/* [jsun] we need to set BAR0 so that SDRAM 0 appears at 0x0 in PCI */
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/* *(long*)0xbfa00218 = 0x8; */
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/* board initialization stuff */
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ddb5476_board_init();
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}
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early_initcall(ddb5476_setup);
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/*
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* We don't trust bios. We essentially does hardware re-initialization
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* as complete as possible, as far as we know we can safely do.
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*/
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static void ddb5476_board_init(void)
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{
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/* ----------- setup PDARs ------------ */
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/* check SDRAM0, whether we are on MEM bus does not matter */
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db_assert((ddb_in32(DDB_SDRAM0) & 0xffffffef) ==
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ddb_calc_pdar(DDB_SDRAM_BASE, DDB_SDRAM_SIZE, 32, 0, 1));
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/* SDRAM1 should be turned off. What is this for anyway ? */
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db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
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/* flash 1&2, DDB status, DDB control */
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ddb_set_pdar(DDB_DCS2, DDB_DCS2_BASE, DDB_DCS2_SIZE, 16, 0, 0);
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ddb_set_pdar(DDB_DCS3, DDB_DCS3_BASE, DDB_DCS3_SIZE, 16, 0, 0);
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ddb_set_pdar(DDB_DCS4, DDB_DCS4_BASE, DDB_DCS4_SIZE, 8, 0, 0);
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ddb_set_pdar(DDB_DCS5, DDB_DCS5_BASE, DDB_DCS5_SIZE, 8, 0, 0);
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/* shut off other pdar so they don't accidentally get into the way */
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ddb_set_pdar(DDB_DCS6, 0xffffffff, 0, 32, 0, 0);
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ddb_set_pdar(DDB_DCS7, 0xffffffff, 0, 32, 0, 0);
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ddb_set_pdar(DDB_DCS8, 0xffffffff, 0, 32, 0, 0);
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/* verify VRC5477 base addr */
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/* don't care about some details */
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db_assert((ddb_in32(DDB_INTCS) & 0xffffff0f) ==
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ddb_calc_pdar(DDB_INTCS_BASE, DDB_INTCS_SIZE, 8, 0, 0));
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/* verify BOOT ROM addr */
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/* don't care about some details */
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db_assert((ddb_in32(DDB_BOOTCS) & 0xffffff0f) ==
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ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
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/* setup PCI windows - window1 for MEM/config, window0 for IO */
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ddb_set_pdar(DDB_PCIW0, DDB_PCI_IO_BASE, DDB_PCI_IO_SIZE, 32, 0, 1);
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ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
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ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1);
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ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32);
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/* ----------- setup PDARs ------------ */
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/* this is problematic - it will reset Aladin which cause we loose
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* serial port, and we don't know how to set up Aladin chip again.
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*/
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// ddb_pci_reset_bus();
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ddb_out32(DDB_BAR0, 0x00000008);
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ddb_out32(DDB_BARC, 0xffffffff);
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ddb_out32(DDB_BARB, 0xffffffff);
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ddb_out32(DDB_BAR1, 0xffffffff);
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ddb_out32(DDB_BAR2, 0xffffffff);
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ddb_out32(DDB_BAR3, 0xffffffff);
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ddb_out32(DDB_BAR4, 0xffffffff);
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ddb_out32(DDB_BAR5, 0xffffffff);
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ddb_out32(DDB_BAR6, 0xffffffff);
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ddb_out32(DDB_BAR7, 0xffffffff);
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ddb_out32(DDB_BAR8, 0xffffffff);
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/* ----------- switch PCI1 to PCI CONFIG space ------------ */
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ddb_set_pdar(DDB_PCIW1, DDB_PCI_CONFIG_BASE, DDB_PCI_CONFIG_SIZE, 32, 0, 1);
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ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_CFG, 0x0, DDB_PCI_ACCESS_32);
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/* ----- M1543 PCI setup ------ */
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/* we know M1543 PCI-ISA controller is at addr:18 */
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/* xxxx1010 makes USB at addr:13 and PMU at addr:14 */
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*(volatile unsigned char *) 0xa8040072 &= 0xf0;
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*(volatile unsigned char *) 0xa8040072 |= 0xa;
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/* setup USB interrupt to IRQ 9, (bit 0:3 - 0001)
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* no IOCHRDY signal, (bit 7 - 1)
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* M1543C & M7101 VID and Subsys Device ID are read-only (bit 6 - 1)
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* Make USB Master INTAJ level to edge conversion (bit 4 - 1)
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*/
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*(unsigned char *) 0xa8040074 = 0xd1;
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/* setup PMU(SCI to IRQ 10 (bit 0:3 - 0011)
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* SCI routing to IRQ 13 disabled (bit 7 - 1)
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* SCI interrupt level to edge conversion bypassed (bit 4 - 0)
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*/
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*(unsigned char *) 0xa8040076 = 0x83;
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/* setup IDE controller
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* enable IDE controller (bit 6 - 1)
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* IDE IDSEL to be addr:24 (bit 4:5 - 11)
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* no IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0)
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* no IDE ATA Primary Bus Signal Pad Control (bit 2 - 0)
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* primary IRQ is 14, secondary is 15 (bit 1:0 - 01
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*/
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// *(unsigned char*)0xa8040058 = 0x71;
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// *(unsigned char*)0xa8040058 = 0x79;
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// *(unsigned char*)0xa8040058 = 0x74; // use SIRQ, primary tri-state
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*(unsigned char *) 0xa8040058 = 0x75; // primary tri-state
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#if 0
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/* this is not necessary if M5229 does not use SIRQ */
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*(unsigned char *) 0xa8040044 = 0x0d; // primary to IRQ 14
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*(unsigned char *) 0xa8040075 = 0x0d; // secondary to IRQ 14
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#endif
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/* enable IDE in the M5229 config register 0x50 (bit 0 - 1) */
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/* M5229 IDSEL is addr:24; see above setting */
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*(unsigned char *) 0xa9000050 |= 0x1;
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/* enable bus master (bit 2) and IO decoding (bit 0) */
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*(unsigned char *) 0xa9000004 |= 0x5;
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/* enable native, copied from arch/ppc/k2boot/head.S */
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/* TODO - need volatile, need to be portable */
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*(unsigned char *) 0xa9000009 = 0xff;
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/* ----- end of M1543 PCI setup ------ */
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/* ----- reset on-board ether chip ------ */
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*((volatile u32 *) 0xa8020004) |= 1; /* decode I/O */
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*((volatile u32 *) 0xa8020010) = 0; /* set BAR address */
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/* send reset command */
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*((volatile u32 *) 0xa6000000) = 1; /* do a soft reset */
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/* disable ether chip */
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*((volatile u32 *) 0xa8020004) = 0; /* disable any decoding */
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/* put it into sleep */
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*((volatile u32 *) 0xa8020040) = 0x80000000;
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/* ----- end of reset on-board ether chip ------ */
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/* ----------- switch PCI1 back to PCI MEM space ------------ */
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ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1);
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ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32);
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}
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