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143 lines
4.5 KiB
143 lines
4.5 KiB
/*
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* arch/mips/ddb5476/irq.c -- NEC DDB Vrc-5476 interrupt routines
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*
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* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
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* Sony Software Development Center Europe (SDCE), Brussels
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*
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* Re-write the whole thing to use new irq.c file.
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* Copyright (C) 2001 MontaVista Software Inc.
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* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
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*
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*/
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <asm/i8259.h>
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#include <asm/io.h>
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#include <asm/ptrace.h>
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#include <asm/ddb5xxx/ddb5xxx.h>
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#define M1543_PNP_CONFIG 0x03f0 /* PnP Config Port */
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#define M1543_PNP_INDEX 0x03f0 /* PnP Index Port */
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#define M1543_PNP_DATA 0x03f1 /* PnP Data Port */
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#define M1543_PNP_ALT_CONFIG 0x0370 /* Alternative PnP Config Port */
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#define M1543_PNP_ALT_INDEX 0x0370 /* Alternative PnP Index Port */
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#define M1543_PNP_ALT_DATA 0x0371 /* Alternative PnP Data Port */
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#define M1543_INT1_MASTER_CTRL 0x0020 /* INT_1 (master) Control Register */
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#define M1543_INT1_MASTER_MASK 0x0021 /* INT_1 (master) Mask Register */
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#define M1543_INT1_SLAVE_CTRL 0x00a0 /* INT_1 (slave) Control Register */
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#define M1543_INT1_SLAVE_MASK 0x00a1 /* INT_1 (slave) Mask Register */
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#define M1543_INT1_MASTER_ELCR 0x04d0 /* INT_1 (master) Edge/Level Control */
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#define M1543_INT1_SLAVE_ELCR 0x04d1 /* INT_1 (slave) Edge/Level Control */
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static void m1543_irq_setup(void)
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{
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/*
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* The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13. Not all
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* the possible IO sources in the M1543 are in use by us. We will
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* use the following mapping:
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*
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* IRQ1 - keyboard (default set by M1543)
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* IRQ3 - reserved for UART B (default set by M1543) (note that
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* the schematics for the DDB Vrc-5476 board seem to
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* indicate that IRQ3 is connected to the DS1386
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* watchdog timer interrupt output so we might have
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* a conflict)
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* IRQ4 - reserved for UART A (default set by M1543)
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* IRQ5 - parallel (default set by M1543)
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* IRQ8 - DS1386 time of day (RTC) interrupt
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* IRQ9 - USB (hardwired in ddb_setup)
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* IRQ10 - PMU (hardwired in ddb_setup)
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* IRQ12 - mouse
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* IRQ14,15 - IDE controller (need to be confirmed, jsun)
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*/
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/*
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* Assing mouse interrupt to IRQ12
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*/
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/* Enter configuration mode */
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outb(0x51, M1543_PNP_CONFIG);
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outb(0x23, M1543_PNP_CONFIG);
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/* Select logical device 7 (Keyboard) */
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outb(0x07, M1543_PNP_INDEX);
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outb(0x07, M1543_PNP_DATA);
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/* Select IRQ12 */
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outb(0x72, M1543_PNP_INDEX);
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outb(0x0c, M1543_PNP_DATA);
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/* Leave configration mode */
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outb(0xbb, M1543_PNP_CONFIG);
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}
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static void nile4_irq_setup(void)
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{
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int i;
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/* Map all interrupts to CPU int #0 (IP2) */
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nile4_map_irq_all(0);
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/* PCI INTA#-E# must be level triggered */
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nile4_set_pci_irq_level_or_edge(0, 1);
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nile4_set_pci_irq_level_or_edge(1, 1);
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nile4_set_pci_irq_level_or_edge(2, 1);
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nile4_set_pci_irq_level_or_edge(3, 1);
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/* PCI INTA#, B#, D# must be active low, INTC# must be active high */
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nile4_set_pci_irq_polarity(0, 0);
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nile4_set_pci_irq_polarity(1, 0);
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nile4_set_pci_irq_polarity(2, 1);
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nile4_set_pci_irq_polarity(3, 0);
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for (i = 0; i < 16; i++)
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nile4_clear_irq(i);
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/* Enable CPU int #0 */
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nile4_enable_irq_output(0);
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/* memory resource acquire in ddb_setup */
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}
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static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
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static struct irqaction irq_error = { no_action, 0, CPU_MASK_NONE, "error", NULL, NULL };
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extern asmlinkage void ddb5476_handle_int(void);
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extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
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extern void mips_cpu_irq_init(u32 irq_base);
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extern void vrc5476_irq_init(u32 irq_base);
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void __init arch_init_irq(void)
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{
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/* hardware initialization */
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nile4_irq_setup();
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m1543_irq_setup();
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/* controller setup */
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init_i8259_irqs();
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vrc5476_irq_init(VRC5476_IRQ_BASE);
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mips_cpu_irq_init(CPU_IRQ_BASE);
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/* setup cascade interrupts */
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setup_irq(VRC5476_IRQ_BASE + VRC5476_I8259_CASCADE, &irq_cascade);
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setup_irq(CPU_IRQ_BASE + CPU_VRC5476_CASCADE, &irq_cascade);
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/* setup error interrupts for debugging */
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setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CPCE, &irq_error);
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setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CNTD, &irq_error);
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setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_MCE, &irq_error);
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setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_LBRT, &irq_error);
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setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCIS, &irq_error);
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setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCI, &irq_error);
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/* setup the grandpa intr vector */
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set_except_vector(0, ddb5476_handle_int);
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}
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