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1053 lines
30 KiB
1053 lines
30 KiB
/*
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* drivers/sbus/char/bpp.c
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*
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* Copyright (c) 1995 Picture Elements
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* Stephen Williams (steve@icarus.com)
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* Gus Baldauf (gbaldauf@ix.netcom.com)
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*
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* Linux/SPARC port by Peter Zaitcev.
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* Integration into SPARC tree by Tom Dyas.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/fs.h>
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/smp_lock.h>
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#include <linux/spinlock.h>
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#include <linux/timer.h>
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#include <linux/ioport.h>
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#include <linux/major.h>
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#include <asm/uaccess.h>
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#include <asm/io.h>
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#if defined(__i386__)
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# include <asm/system.h>
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#endif
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#if defined(__sparc__)
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# include <linux/init.h>
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# include <linux/delay.h> /* udelay() */
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# include <asm/oplib.h> /* OpenProm Library */
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# include <asm/sbus.h>
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#endif
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#include <asm/bpp.h>
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#define BPP_PROBE_CODE 0x55
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#define BPP_DELAY 100
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static const unsigned BPP_MAJOR = LP_MAJOR;
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static const char* dev_name = "bpp";
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/* When switching from compatibility to a mode where I can read, try
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the following mode first. */
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/* const unsigned char DEFAULT_ECP = 0x10; */
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static const unsigned char DEFAULT_ECP = 0x30;
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static const unsigned char DEFAULT_NIBBLE = 0x00;
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/*
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* These are 1284 time constraints, in units of jiffies.
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*/
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static const unsigned long TIME_PSetup = 1;
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static const unsigned long TIME_PResponse = 6;
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static const unsigned long TIME_IDLE_LIMIT = 2000;
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/*
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* One instance per supported subdevice...
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*/
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# define BPP_NO 3
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enum IEEE_Mode { COMPATIBILITY, NIBBLE, ECP, ECP_RLE, EPP };
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struct inst {
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unsigned present : 1; /* True if the hardware exists */
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unsigned enhanced : 1; /* True if the hardware in "enhanced" */
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unsigned opened : 1; /* True if the device is opened already */
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unsigned run_flag : 1; /* True if waiting for a repeate byte */
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unsigned char direction; /* 0 --> out, 0x20 --> IN */
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unsigned char pp_state; /* State of host controlled pins. */
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enum IEEE_Mode mode;
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unsigned char run_length;
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unsigned char repeat_byte;
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};
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static struct inst instances[BPP_NO];
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#if defined(__i386__)
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static const unsigned short base_addrs[BPP_NO] = { 0x278, 0x378, 0x3bc };
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/*
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* These are for data access.
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* Control lines accesses are hidden in set_bits() and get_bits().
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* The exception is the probe procedure, which is system-dependent.
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*/
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#define bpp_outb_p(data, base) outb_p((data), (base))
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#define bpp_inb(base) inb(base)
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#define bpp_inb_p(base) inb_p(base)
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/*
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* This method takes the pin values mask and sets the hardware pins to
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* the requested value: 1 == high voltage, 0 == low voltage. This
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* burries the annoying PC bit inversion and preserves the direction
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* flag.
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*/
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static void set_pins(unsigned short pins, unsigned minor)
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{
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unsigned char bits = instances[minor].direction; /* == 0x20 */
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if (! (pins & BPP_PP_nStrobe)) bits |= 1;
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if (! (pins & BPP_PP_nAutoFd)) bits |= 2;
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if ( pins & BPP_PP_nInit) bits |= 4;
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if (! (pins & BPP_PP_nSelectIn)) bits |= 8;
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instances[minor].pp_state = bits;
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outb_p(bits, base_addrs[minor]+2);
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}
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static unsigned short get_pins(unsigned minor)
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{
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unsigned short bits = 0;
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unsigned value = instances[minor].pp_state;
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if (! (value & 0x01)) bits |= BPP_PP_nStrobe;
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if (! (value & 0x02)) bits |= BPP_PP_nAutoFd;
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if (value & 0x04) bits |= BPP_PP_nInit;
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if (! (value & 0x08)) bits |= BPP_PP_nSelectIn;
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value = inb_p(base_addrs[minor]+1);
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if (value & 0x08) bits |= BPP_GP_nFault;
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if (value & 0x10) bits |= BPP_GP_Select;
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if (value & 0x20) bits |= BPP_GP_PError;
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if (value & 0x40) bits |= BPP_GP_nAck;
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if (! (value & 0x80)) bits |= BPP_GP_Busy;
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return bits;
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}
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#endif /* __i386__ */
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#if defined(__sparc__)
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/*
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* Register block
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*/
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/* DMA registers */
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#define BPP_CSR 0x00
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#define BPP_ADDR 0x04
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#define BPP_BCNT 0x08
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#define BPP_TST_CSR 0x0C
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/* Parallel Port registers */
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#define BPP_HCR 0x10
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#define BPP_OCR 0x12
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#define BPP_DR 0x14
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#define BPP_TCR 0x15
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#define BPP_OR 0x16
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#define BPP_IR 0x17
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#define BPP_ICR 0x18
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#define BPP_SIZE 0x1A
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/* BPP_CSR. Bits of type RW1 are cleared with writting '1'. */
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#define P_DEV_ID_MASK 0xf0000000 /* R */
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#define P_DEV_ID_ZEBRA 0x40000000
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#define P_DEV_ID_L64854 0xa0000000 /* == NCR 89C100+89C105. Pity. */
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#define P_NA_LOADED 0x08000000 /* R NA wirtten but was not used */
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#define P_A_LOADED 0x04000000 /* R */
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#define P_DMA_ON 0x02000000 /* R DMA is not disabled */
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#define P_EN_NEXT 0x01000000 /* RW */
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#define P_TCI_DIS 0x00800000 /* RW TCI forbidden from interrupts */
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#define P_DIAG 0x00100000 /* RW Disables draining and resetting
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of P-FIFO on loading of P_ADDR*/
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#define P_BURST_SIZE 0x000c0000 /* RW SBus burst size */
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#define P_BURST_8 0x00000000
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#define P_BURST_4 0x00040000
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#define P_BURST_1 0x00080000 /* "No burst" write */
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#define P_TC 0x00004000 /* RW1 Term Count, can be cleared when
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P_EN_NEXT=1 */
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#define P_EN_CNT 0x00002000 /* RW */
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#define P_EN_DMA 0x00000200 /* RW */
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#define P_WRITE 0x00000100 /* R DMA dir, 1=to ram, 0=to port */
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#define P_RESET 0x00000080 /* RW */
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#define P_SLAVE_ERR 0x00000040 /* RW1 Access size error */
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#define P_INVALIDATE 0x00000020 /* W Drop P-FIFO */
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#define P_INT_EN 0x00000010 /* RW OK to P_INT_PEND||P_ERR_PEND */
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#define P_DRAINING 0x0000000c /* R P-FIFO is draining to memory */
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#define P_ERR_PEND 0x00000002 /* R */
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#define P_INT_PEND 0x00000001 /* R */
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/* BPP_HCR. Time is in increments of SBus clock. */
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#define P_HCR_TEST 0x8000 /* Allows buried counters to be read */
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#define P_HCR_DSW 0x7f00 /* Data strobe width (in ticks) */
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#define P_HCR_DDS 0x007f /* Data setup before strobe (in ticks) */
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/* BPP_OCR. */
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#define P_OCR_MEM_CLR 0x8000
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#define P_OCR_DATA_SRC 0x4000 /* ) */
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#define P_OCR_DS_DSEL 0x2000 /* ) Bidirectional */
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#define P_OCR_BUSY_DSEL 0x1000 /* ) selects */
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#define P_OCR_ACK_DSEL 0x0800 /* ) */
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#define P_OCR_EN_DIAG 0x0400
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#define P_OCR_BUSY_OP 0x0200 /* Busy operation */
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#define P_OCR_ACK_OP 0x0100 /* Ack operation */
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#define P_OCR_SRST 0x0080 /* Reset state machines. Not selfcleaning. */
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#define P_OCR_IDLE 0x0008 /* PP data transfer state machine is idle */
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#define P_OCR_V_ILCK 0x0002 /* Versatec faded. Zebra only. */
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#define P_OCR_EN_VER 0x0001 /* Enable Versatec (0 - enable). Zebra only. */
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/* BPP_TCR */
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#define P_TCR_DIR 0x08
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#define P_TCR_BUSY 0x04
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#define P_TCR_ACK 0x02
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#define P_TCR_DS 0x01 /* Strobe */
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/* BPP_OR */
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#define P_OR_V3 0x20 /* ) */
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#define P_OR_V2 0x10 /* ) on Zebra only */
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#define P_OR_V1 0x08 /* ) */
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#define P_OR_INIT 0x04
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#define P_OR_AFXN 0x02 /* Auto Feed */
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#define P_OR_SLCT_IN 0x01
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/* BPP_IR */
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#define P_IR_PE 0x04
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#define P_IR_SLCT 0x02
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#define P_IR_ERR 0x01
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/* BPP_ICR */
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#define P_DS_IRQ 0x8000 /* RW1 */
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#define P_ACK_IRQ 0x4000 /* RW1 */
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#define P_BUSY_IRQ 0x2000 /* RW1 */
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#define P_PE_IRQ 0x1000 /* RW1 */
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#define P_SLCT_IRQ 0x0800 /* RW1 */
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#define P_ERR_IRQ 0x0400 /* RW1 */
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#define P_DS_IRQ_EN 0x0200 /* RW Always on rising edge */
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#define P_ACK_IRQ_EN 0x0100 /* RW Always on rising edge */
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#define P_BUSY_IRP 0x0080 /* RW 1= rising edge */
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#define P_BUSY_IRQ_EN 0x0040 /* RW */
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#define P_PE_IRP 0x0020 /* RW 1= rising edge */
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#define P_PE_IRQ_EN 0x0010 /* RW */
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#define P_SLCT_IRP 0x0008 /* RW 1= rising edge */
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#define P_SLCT_IRQ_EN 0x0004 /* RW */
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#define P_ERR_IRP 0x0002 /* RW1 1= rising edge */
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#define P_ERR_IRQ_EN 0x0001 /* RW */
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static void __iomem *base_addrs[BPP_NO];
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#define bpp_outb_p(data, base) sbus_writeb(data, (base) + BPP_DR)
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#define bpp_inb_p(base) sbus_readb((base) + BPP_DR)
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#define bpp_inb(base) sbus_readb((base) + BPP_DR)
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static void set_pins(unsigned short pins, unsigned minor)
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{
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void __iomem *base = base_addrs[minor];
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unsigned char bits_tcr = 0, bits_or = 0;
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if (instances[minor].direction & 0x20) bits_tcr |= P_TCR_DIR;
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if ( pins & BPP_PP_nStrobe) bits_tcr |= P_TCR_DS;
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if ( pins & BPP_PP_nAutoFd) bits_or |= P_OR_AFXN;
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if (! (pins & BPP_PP_nInit)) bits_or |= P_OR_INIT;
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if (! (pins & BPP_PP_nSelectIn)) bits_or |= P_OR_SLCT_IN;
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sbus_writeb(bits_or, base + BPP_OR);
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sbus_writeb(bits_tcr, base + BPP_TCR);
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}
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/*
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* i386 people read output pins from a software image.
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* We may get them back from hardware.
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* Again, inversion of pins must he buried here.
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*/
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static unsigned short get_pins(unsigned minor)
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{
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void __iomem *base = base_addrs[minor];
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unsigned short bits = 0;
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unsigned value_tcr = sbus_readb(base + BPP_TCR);
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unsigned value_ir = sbus_readb(base + BPP_IR);
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unsigned value_or = sbus_readb(base + BPP_OR);
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if (value_tcr & P_TCR_DS) bits |= BPP_PP_nStrobe;
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if (value_or & P_OR_AFXN) bits |= BPP_PP_nAutoFd;
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if (! (value_or & P_OR_INIT)) bits |= BPP_PP_nInit;
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if (! (value_or & P_OR_SLCT_IN)) bits |= BPP_PP_nSelectIn;
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if (value_ir & P_IR_ERR) bits |= BPP_GP_nFault;
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if (! (value_ir & P_IR_SLCT)) bits |= BPP_GP_Select;
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if (! (value_ir & P_IR_PE)) bits |= BPP_GP_PError;
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if (! (value_tcr & P_TCR_ACK)) bits |= BPP_GP_nAck;
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if (value_tcr & P_TCR_BUSY) bits |= BPP_GP_Busy;
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return bits;
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}
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#endif /* __sparc__ */
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static void snooze(unsigned long snooze_time, unsigned minor)
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{
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schedule_timeout_uninterruptible(snooze_time + 1);
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}
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static int wait_for(unsigned short set, unsigned short clr,
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unsigned long delay, unsigned minor)
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{
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unsigned short pins = get_pins(minor);
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unsigned long extime = 0;
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/*
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* Try a real fast scan for the first jiffy, in case the device
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* responds real good. The first while loop guesses an expire
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* time accounting for possible wraparound of jiffies.
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*/
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while (time_after_eq(jiffies, extime)) extime = jiffies + 1;
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while ( (time_before(jiffies, extime))
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&& (((pins & set) != set) || ((pins & clr) != 0)) ) {
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pins = get_pins(minor);
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}
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delay -= 1;
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/*
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* If my delay expired or the pins are still not where I want
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* them, then resort to using the timer and greatly reduce my
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* sample rate. If the peripheral is going to be slow, this will
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* give the CPU up to some more worthy process.
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*/
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while ( delay && (((pins & set) != set) || ((pins & clr) != 0)) ) {
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snooze(1, minor);
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pins = get_pins(minor);
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delay -= 1;
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}
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if (delay == 0) return -1;
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else return pins;
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}
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/*
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* Return ZERO(0) If the negotiation succeeds, an errno otherwise. An
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* errno means something broke, and I do not yet know how to fix it.
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*/
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static int negotiate(unsigned char mode, unsigned minor)
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{
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int rc;
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unsigned short pins = get_pins(minor);
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if (pins & BPP_PP_nSelectIn) return -EIO;
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/* Event 0: Write the mode to the data lines */
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bpp_outb_p(mode, base_addrs[minor]);
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snooze(TIME_PSetup, minor);
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/* Event 1: Strobe the mode code into the peripheral */
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set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe|BPP_PP_nInit, minor);
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/* Wait for Event 2: Peripheral responds as a 1284 device. */
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rc = wait_for(BPP_GP_PError|BPP_GP_Select|BPP_GP_nFault,
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BPP_GP_nAck,
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TIME_PResponse,
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minor);
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if (rc == -1) return -ETIMEDOUT;
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/* Event 3: latch extensibility request */
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set_pins(BPP_PP_nSelectIn|BPP_PP_nInit, minor);
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/* ... quick nap while peripheral ponders the byte i'm sending...*/
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snooze(1, minor);
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/* Event 4: restore strobe, to ACK peripheral's response. */
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set_pins(BPP_PP_nSelectIn|BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
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/* Wait for Event 6: Peripheral latches response bits */
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rc = wait_for(BPP_GP_nAck, 0, TIME_PSetup+TIME_PResponse, minor);
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if (rc == -1) return -EIO;
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/* A 1284 device cannot refuse nibble mode */
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if (mode == DEFAULT_NIBBLE) return 0;
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if (pins & BPP_GP_Select) return 0;
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return -EPROTONOSUPPORT;
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}
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static int terminate(unsigned minor)
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{
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int rc;
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/* Event 22: Request termination of 1284 mode */
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set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
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/* Wait for Events 23 and 24: ACK termination request. */
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rc = wait_for(BPP_GP_Busy|BPP_GP_nFault,
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BPP_GP_nAck,
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TIME_PSetup+TIME_PResponse,
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minor);
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instances[minor].direction = 0;
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instances[minor].mode = COMPATIBILITY;
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if (rc == -1) {
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return -EIO;
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}
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/* Event 25: Handshake by lowering nAutoFd */
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set_pins(BPP_PP_nStrobe|BPP_PP_nInit, minor);
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/* Event 26: Peripheral wiggles lines... */
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/* Event 27: Peripheral sets nAck HIGH to ack handshake */
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rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
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if (rc == -1) {
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set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
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return -EIO;
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}
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/* Event 28: Finish phase by raising nAutoFd */
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set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
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return 0;
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}
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static DEFINE_SPINLOCK(bpp_open_lock);
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/*
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* Allow only one process to open the device at a time.
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*/
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static int bpp_open(struct inode *inode, struct file *f)
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{
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unsigned minor = iminor(inode);
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int ret;
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spin_lock(&bpp_open_lock);
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ret = 0;
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if (minor >= BPP_NO) {
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ret = -ENODEV;
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} else {
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if (! instances[minor].present) {
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ret = -ENODEV;
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} else {
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if (instances[minor].opened)
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ret = -EBUSY;
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else
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instances[minor].opened = 1;
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}
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}
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spin_unlock(&bpp_open_lock);
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return ret;
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}
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/*
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* When the process closes the device, this method is called to clean
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* up and reset the hardware. Always leave the device in compatibility
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* mode as this is a reasonable place to clean up from messes made by
|
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* ioctls, or other mayhem.
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*/
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static int bpp_release(struct inode *inode, struct file *f)
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{
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unsigned minor = iminor(inode);
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|
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spin_lock(&bpp_open_lock);
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instances[minor].opened = 0;
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|
if (instances[minor].mode != COMPATIBILITY)
|
|
terminate(minor);
|
|
|
|
spin_unlock(&bpp_open_lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static long read_nibble(unsigned minor, char __user *c, unsigned long cnt)
|
|
{
|
|
unsigned long remaining = cnt;
|
|
long rc;
|
|
|
|
while (remaining > 0) {
|
|
unsigned char byte = 0;
|
|
int pins;
|
|
|
|
/* Event 7: request nibble */
|
|
set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe, minor);
|
|
|
|
/* Wait for event 9: Peripher strobes first nibble */
|
|
pins = wait_for(0, BPP_GP_nAck, TIME_IDLE_LIMIT, minor);
|
|
if (pins == -1) return -ETIMEDOUT;
|
|
|
|
/* Event 10: I handshake nibble */
|
|
set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe|BPP_PP_nAutoFd, minor);
|
|
if (pins & BPP_GP_nFault) byte |= 0x01;
|
|
if (pins & BPP_GP_Select) byte |= 0x02;
|
|
if (pins & BPP_GP_PError) byte |= 0x04;
|
|
if (pins & BPP_GP_Busy) byte |= 0x08;
|
|
|
|
/* Wait for event 11: Peripheral handshakes nibble */
|
|
rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
|
|
|
|
/* Event 7: request nibble */
|
|
set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe, minor);
|
|
|
|
/* Wait for event 9: Peripher strobes first nibble */
|
|
pins = wait_for(0, BPP_GP_nAck, TIME_PResponse, minor);
|
|
if (rc == -1) return -ETIMEDOUT;
|
|
|
|
/* Event 10: I handshake nibble */
|
|
set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe|BPP_PP_nAutoFd, minor);
|
|
if (pins & BPP_GP_nFault) byte |= 0x10;
|
|
if (pins & BPP_GP_Select) byte |= 0x20;
|
|
if (pins & BPP_GP_PError) byte |= 0x40;
|
|
if (pins & BPP_GP_Busy) byte |= 0x80;
|
|
|
|
if (put_user(byte, c))
|
|
return -EFAULT;
|
|
c += 1;
|
|
remaining -= 1;
|
|
|
|
/* Wait for event 11: Peripheral handshakes nibble */
|
|
rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
|
|
if (rc == -1) return -EIO;
|
|
}
|
|
|
|
return cnt - remaining;
|
|
}
|
|
|
|
static long read_ecp(unsigned minor, char __user *c, unsigned long cnt)
|
|
{
|
|
unsigned long remaining;
|
|
long rc;
|
|
|
|
/* Turn ECP mode from forward to reverse if needed. */
|
|
if (! instances[minor].direction) {
|
|
unsigned short pins = get_pins(minor);
|
|
|
|
/* Event 38: Turn the bus around */
|
|
instances[minor].direction = 0x20;
|
|
pins &= ~BPP_PP_nAutoFd;
|
|
set_pins(pins, minor);
|
|
|
|
/* Event 39: Set pins for reverse mode. */
|
|
snooze(TIME_PSetup, minor);
|
|
set_pins(BPP_PP_nStrobe|BPP_PP_nSelectIn, minor);
|
|
|
|
/* Wait for event 40: Peripheral ready to be strobed */
|
|
rc = wait_for(0, BPP_GP_PError, TIME_PResponse, minor);
|
|
if (rc == -1) return -ETIMEDOUT;
|
|
}
|
|
|
|
remaining = cnt;
|
|
|
|
while (remaining > 0) {
|
|
|
|
/* If there is a run length for a repeated byte, repeat */
|
|
/* that byte a few times. */
|
|
if (instances[minor].run_length && !instances[minor].run_flag) {
|
|
|
|
char buffer[128];
|
|
unsigned idx;
|
|
unsigned repeat = remaining < instances[minor].run_length
|
|
? remaining
|
|
: instances[minor].run_length;
|
|
|
|
for (idx = 0 ; idx < repeat ; idx += 1)
|
|
buffer[idx] = instances[minor].repeat_byte;
|
|
|
|
if (copy_to_user(c, buffer, repeat))
|
|
return -EFAULT;
|
|
remaining -= repeat;
|
|
c += repeat;
|
|
instances[minor].run_length -= repeat;
|
|
}
|
|
|
|
if (remaining == 0) break;
|
|
|
|
|
|
/* Wait for Event 43: Data active on the bus. */
|
|
rc = wait_for(0, BPP_GP_nAck, TIME_IDLE_LIMIT, minor);
|
|
if (rc == -1) break;
|
|
|
|
if (rc & BPP_GP_Busy) {
|
|
/* OK, this is data. read it in. */
|
|
unsigned char byte = bpp_inb(base_addrs[minor]);
|
|
if (put_user(byte, c))
|
|
return -EFAULT;
|
|
c += 1;
|
|
remaining -= 1;
|
|
|
|
if (instances[minor].run_flag) {
|
|
instances[minor].repeat_byte = byte;
|
|
instances[minor].run_flag = 0;
|
|
}
|
|
|
|
} else {
|
|
unsigned char byte = bpp_inb(base_addrs[minor]);
|
|
if (byte & 0x80) {
|
|
printk("bpp%d: "
|
|
"Ignoring ECP channel %u from device.\n",
|
|
minor, byte & 0x7f);
|
|
} else {
|
|
instances[minor].run_length = byte;
|
|
instances[minor].run_flag = 1;
|
|
}
|
|
}
|
|
|
|
/* Event 44: I got it. */
|
|
set_pins(BPP_PP_nStrobe|BPP_PP_nAutoFd|BPP_PP_nSelectIn, minor);
|
|
|
|
/* Wait for event 45: peripheral handshake */
|
|
rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
|
|
if (rc == -1) return -ETIMEDOUT;
|
|
|
|
/* Event 46: Finish handshake */
|
|
set_pins(BPP_PP_nStrobe|BPP_PP_nSelectIn, minor);
|
|
|
|
}
|
|
|
|
|
|
return cnt - remaining;
|
|
}
|
|
|
|
static ssize_t bpp_read(struct file *f, char __user *c, size_t cnt, loff_t * ppos)
|
|
{
|
|
long rc;
|
|
unsigned minor = iminor(f->f_path.dentry->d_inode);
|
|
if (minor >= BPP_NO) return -ENODEV;
|
|
if (!instances[minor].present) return -ENODEV;
|
|
|
|
switch (instances[minor].mode) {
|
|
|
|
default:
|
|
if (instances[minor].mode != COMPATIBILITY)
|
|
terminate(minor);
|
|
|
|
if (instances[minor].enhanced) {
|
|
/* For now, do all reads with ECP-RLE mode */
|
|
unsigned short pins;
|
|
|
|
rc = negotiate(DEFAULT_ECP, minor);
|
|
if (rc < 0) break;
|
|
|
|
instances[minor].mode = ECP_RLE;
|
|
|
|
/* Event 30: set nAutoFd low to setup for ECP mode */
|
|
pins = get_pins(minor);
|
|
pins &= ~BPP_PP_nAutoFd;
|
|
set_pins(pins, minor);
|
|
|
|
/* Wait for Event 31: peripheral ready */
|
|
rc = wait_for(BPP_GP_PError, 0, TIME_PResponse, minor);
|
|
if (rc == -1) return -ETIMEDOUT;
|
|
|
|
rc = read_ecp(minor, c, cnt);
|
|
|
|
} else {
|
|
rc = negotiate(DEFAULT_NIBBLE, minor);
|
|
if (rc < 0) break;
|
|
|
|
instances[minor].mode = NIBBLE;
|
|
|
|
rc = read_nibble(minor, c, cnt);
|
|
}
|
|
break;
|
|
|
|
case NIBBLE:
|
|
rc = read_nibble(minor, c, cnt);
|
|
break;
|
|
|
|
case ECP:
|
|
case ECP_RLE:
|
|
rc = read_ecp(minor, c, cnt);
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
return rc;
|
|
}
|
|
|
|
/*
|
|
* Compatibility mode handshaking is a matter of writing data,
|
|
* strobing it, and waiting for the printer to stop being busy.
|
|
*/
|
|
static long write_compat(unsigned minor, const char __user *c, unsigned long cnt)
|
|
{
|
|
long rc;
|
|
unsigned short pins = get_pins(minor);
|
|
|
|
unsigned long remaining = cnt;
|
|
|
|
|
|
while (remaining > 0) {
|
|
unsigned char byte;
|
|
|
|
if (get_user(byte, c))
|
|
return -EFAULT;
|
|
c += 1;
|
|
|
|
rc = wait_for(BPP_GP_nAck, BPP_GP_Busy, TIME_IDLE_LIMIT, minor);
|
|
if (rc == -1) return -ETIMEDOUT;
|
|
|
|
bpp_outb_p(byte, base_addrs[minor]);
|
|
remaining -= 1;
|
|
/* snooze(1, minor); */
|
|
|
|
pins &= ~BPP_PP_nStrobe;
|
|
set_pins(pins, minor);
|
|
|
|
rc = wait_for(BPP_GP_Busy, 0, TIME_PResponse, minor);
|
|
|
|
pins |= BPP_PP_nStrobe;
|
|
set_pins(pins, minor);
|
|
}
|
|
|
|
return cnt - remaining;
|
|
}
|
|
|
|
/*
|
|
* Write data using ECP mode. Watch out that the port may be set up
|
|
* for reading. If so, turn the port around.
|
|
*/
|
|
static long write_ecp(unsigned minor, const char __user *c, unsigned long cnt)
|
|
{
|
|
unsigned short pins = get_pins(minor);
|
|
unsigned long remaining = cnt;
|
|
|
|
if (instances[minor].direction) {
|
|
int rc;
|
|
|
|
/* Event 47 Request bus be turned around */
|
|
pins |= BPP_PP_nInit;
|
|
set_pins(pins, minor);
|
|
|
|
/* Wait for Event 49: Peripheral relinquished bus */
|
|
rc = wait_for(BPP_GP_PError, 0, TIME_PResponse, minor);
|
|
|
|
pins |= BPP_PP_nAutoFd;
|
|
instances[minor].direction = 0;
|
|
set_pins(pins, minor);
|
|
}
|
|
|
|
while (remaining > 0) {
|
|
unsigned char byte;
|
|
int rc;
|
|
|
|
if (get_user(byte, c))
|
|
return -EFAULT;
|
|
|
|
rc = wait_for(0, BPP_GP_Busy, TIME_PResponse, minor);
|
|
if (rc == -1) return -ETIMEDOUT;
|
|
|
|
c += 1;
|
|
|
|
bpp_outb_p(byte, base_addrs[minor]);
|
|
|
|
pins &= ~BPP_PP_nStrobe;
|
|
set_pins(pins, minor);
|
|
|
|
pins |= BPP_PP_nStrobe;
|
|
rc = wait_for(BPP_GP_Busy, 0, TIME_PResponse, minor);
|
|
if (rc == -1) return -EIO;
|
|
|
|
set_pins(pins, minor);
|
|
}
|
|
|
|
return cnt - remaining;
|
|
}
|
|
|
|
/*
|
|
* Write to the peripheral. Be sensitive of the current mode. If I'm
|
|
* in a mode that can be turned around (ECP) then just do
|
|
* that. Otherwise, terminate and do my writing in compat mode. This
|
|
* is the safest course as any device can handle it.
|
|
*/
|
|
static ssize_t bpp_write(struct file *f, const char __user *c, size_t cnt, loff_t * ppos)
|
|
{
|
|
long errno = 0;
|
|
unsigned minor = iminor(f->f_path.dentry->d_inode);
|
|
if (minor >= BPP_NO) return -ENODEV;
|
|
if (!instances[minor].present) return -ENODEV;
|
|
|
|
switch (instances[minor].mode) {
|
|
|
|
case ECP:
|
|
case ECP_RLE:
|
|
errno = write_ecp(minor, c, cnt);
|
|
break;
|
|
case COMPATIBILITY:
|
|
errno = write_compat(minor, c, cnt);
|
|
break;
|
|
default:
|
|
terminate(minor);
|
|
errno = write_compat(minor, c, cnt);
|
|
}
|
|
|
|
return errno;
|
|
}
|
|
|
|
static int bpp_ioctl(struct inode *inode, struct file *f, unsigned int cmd,
|
|
unsigned long arg)
|
|
{
|
|
int errno = 0;
|
|
|
|
unsigned minor = iminor(inode);
|
|
if (minor >= BPP_NO) return -ENODEV;
|
|
if (!instances[minor].present) return -ENODEV;
|
|
|
|
|
|
switch (cmd) {
|
|
|
|
case BPP_PUT_PINS:
|
|
set_pins(arg, minor);
|
|
break;
|
|
|
|
case BPP_GET_PINS:
|
|
errno = get_pins(minor);
|
|
break;
|
|
|
|
case BPP_PUT_DATA:
|
|
bpp_outb_p(arg, base_addrs[minor]);
|
|
break;
|
|
|
|
case BPP_GET_DATA:
|
|
errno = bpp_inb_p(base_addrs[minor]);
|
|
break;
|
|
|
|
case BPP_SET_INPUT:
|
|
if (arg)
|
|
if (instances[minor].enhanced) {
|
|
unsigned short bits = get_pins(minor);
|
|
instances[minor].direction = 0x20;
|
|
set_pins(bits, minor);
|
|
} else {
|
|
errno = -ENOTTY;
|
|
}
|
|
else {
|
|
unsigned short bits = get_pins(minor);
|
|
instances[minor].direction = 0x00;
|
|
set_pins(bits, minor);
|
|
}
|
|
break;
|
|
|
|
default:
|
|
errno = -EINVAL;
|
|
}
|
|
|
|
return errno;
|
|
}
|
|
|
|
static const struct file_operations bpp_fops = {
|
|
.owner = THIS_MODULE,
|
|
.read = bpp_read,
|
|
.write = bpp_write,
|
|
.ioctl = bpp_ioctl,
|
|
.open = bpp_open,
|
|
.release = bpp_release,
|
|
};
|
|
|
|
#if defined(__i386__)
|
|
|
|
#define collectLptPorts() {}
|
|
|
|
static void probeLptPort(unsigned idx)
|
|
{
|
|
unsigned int testvalue;
|
|
const unsigned short lpAddr = base_addrs[idx];
|
|
|
|
instances[idx].present = 0;
|
|
instances[idx].enhanced = 0;
|
|
instances[idx].direction = 0;
|
|
instances[idx].mode = COMPATIBILITY;
|
|
instances[idx].run_length = 0;
|
|
instances[idx].run_flag = 0;
|
|
if (!request_region(lpAddr,3, dev_name)) return;
|
|
|
|
/*
|
|
* First, make sure the instance exists. Do this by writing to
|
|
* the data latch and reading the value back. If the port *is*
|
|
* present, test to see if it supports extended-mode
|
|
* operation. This will be required for IEEE1284 reverse
|
|
* transfers.
|
|
*/
|
|
|
|
outb_p(BPP_PROBE_CODE, lpAddr);
|
|
for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
|
|
;
|
|
testvalue = inb_p(lpAddr);
|
|
if (testvalue == BPP_PROBE_CODE) {
|
|
unsigned save;
|
|
instances[idx].present = 1;
|
|
|
|
save = inb_p(lpAddr+2);
|
|
for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
|
|
;
|
|
outb_p(save|0x20, lpAddr+2);
|
|
for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
|
|
;
|
|
outb_p(~BPP_PROBE_CODE, lpAddr);
|
|
for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
|
|
;
|
|
testvalue = inb_p(lpAddr);
|
|
if ((testvalue&0xff) == (0xff&~BPP_PROBE_CODE))
|
|
instances[idx].enhanced = 0;
|
|
else
|
|
instances[idx].enhanced = 1;
|
|
outb_p(save, lpAddr+2);
|
|
}
|
|
else {
|
|
release_region(lpAddr,3);
|
|
}
|
|
/*
|
|
* Leave the port in compat idle mode.
|
|
*/
|
|
set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, idx);
|
|
|
|
printk("bpp%d: Port at 0x%03x: Enhanced mode %s\n", idx, base_addrs[idx],
|
|
instances[idx].enhanced? "SUPPORTED" : "UNAVAILABLE");
|
|
}
|
|
|
|
static inline void freeLptPort(int idx)
|
|
{
|
|
release_region(base_addrs[idx], 3);
|
|
}
|
|
|
|
#endif
|
|
|
|
#if defined(__sparc__)
|
|
|
|
static void __iomem *map_bpp(struct sbus_dev *dev, int idx)
|
|
{
|
|
return sbus_ioremap(&dev->resource[0], 0, BPP_SIZE, "bpp");
|
|
}
|
|
|
|
static int collectLptPorts(void)
|
|
{
|
|
struct sbus_bus *bus;
|
|
struct sbus_dev *dev;
|
|
int count;
|
|
|
|
count = 0;
|
|
for_all_sbusdev(dev, bus) {
|
|
if (strcmp(dev->prom_name, "SUNW,bpp") == 0) {
|
|
if (count >= BPP_NO) {
|
|
printk(KERN_NOTICE
|
|
"bpp: More than %d bpp ports,"
|
|
" rest is ignored\n", BPP_NO);
|
|
return count;
|
|
}
|
|
base_addrs[count] = map_bpp(dev, count);
|
|
count++;
|
|
}
|
|
}
|
|
return count;
|
|
}
|
|
|
|
static void probeLptPort(unsigned idx)
|
|
{
|
|
void __iomem *rp = base_addrs[idx];
|
|
__u32 csr;
|
|
char *brand;
|
|
|
|
instances[idx].present = 0;
|
|
instances[idx].enhanced = 0;
|
|
instances[idx].direction = 0;
|
|
instances[idx].mode = COMPATIBILITY;
|
|
instances[idx].run_length = 0;
|
|
instances[idx].run_flag = 0;
|
|
|
|
if (!rp) return;
|
|
|
|
instances[idx].present = 1;
|
|
instances[idx].enhanced = 1; /* Sure */
|
|
|
|
csr = sbus_readl(rp + BPP_CSR);
|
|
if ((csr & P_DRAINING) != 0 && (csr & P_ERR_PEND) == 0) {
|
|
udelay(20);
|
|
csr = sbus_readl(rp + BPP_CSR);
|
|
if ((csr & P_DRAINING) != 0 && (csr & P_ERR_PEND) == 0) {
|
|
printk("bpp%d: DRAINING still active (0x%08x)\n", idx, csr);
|
|
}
|
|
}
|
|
printk("bpp%d: reset with 0x%08x ..", idx, csr);
|
|
sbus_writel((csr | P_RESET) & ~P_INT_EN, rp + BPP_CSR);
|
|
udelay(500);
|
|
sbus_writel(sbus_readl(rp + BPP_CSR) & ~P_RESET, rp + BPP_CSR);
|
|
csr = sbus_readl(rp + BPP_CSR);
|
|
printk(" done with csr=0x%08x ocr=0x%04x\n",
|
|
csr, sbus_readw(rp + BPP_OCR));
|
|
|
|
switch (csr & P_DEV_ID_MASK) {
|
|
case P_DEV_ID_ZEBRA:
|
|
brand = "Zebra";
|
|
break;
|
|
case P_DEV_ID_L64854:
|
|
brand = "DMA2";
|
|
break;
|
|
default:
|
|
brand = "Unknown";
|
|
}
|
|
printk("bpp%d: %s at %p\n", idx, brand, rp);
|
|
|
|
/*
|
|
* Leave the port in compat idle mode.
|
|
*/
|
|
set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, idx);
|
|
|
|
return;
|
|
}
|
|
|
|
static inline void freeLptPort(int idx)
|
|
{
|
|
sbus_iounmap(base_addrs[idx], BPP_SIZE);
|
|
}
|
|
|
|
#endif
|
|
|
|
static int __init bpp_init(void)
|
|
{
|
|
int rc;
|
|
unsigned idx;
|
|
|
|
rc = collectLptPorts();
|
|
if (rc == 0)
|
|
return -ENODEV;
|
|
|
|
rc = register_chrdev(BPP_MAJOR, dev_name, &bpp_fops);
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
for (idx = 0; idx < BPP_NO; idx++) {
|
|
instances[idx].opened = 0;
|
|
probeLptPort(idx);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __exit bpp_cleanup(void)
|
|
{
|
|
unsigned idx;
|
|
|
|
unregister_chrdev(BPP_MAJOR, dev_name);
|
|
|
|
for (idx = 0; idx < BPP_NO; idx++) {
|
|
if (instances[idx].present)
|
|
freeLptPort(idx);
|
|
}
|
|
}
|
|
|
|
module_init(bpp_init);
|
|
module_exit(bpp_cleanup);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
|