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135 lines
3.3 KiB
135 lines
3.3 KiB
/*
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* Atheros AR913X/AR933X SoC built-in WMAC device support
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*
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* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Atheros 2.6.15/2.6.31 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/platform_device.h>
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#include <linux/ath9k_platform.h>
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#include <asm/mach-ath79/ath79.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "dev-wmac.h"
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static struct ath9k_platform_data ath79_wmac_data;
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static struct resource ath79_wmac_resources[] = {
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{
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/* .start and .end fields are filled dynamically */
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.flags = IORESOURCE_MEM,
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}, {
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/* .start and .end fields are filled dynamically */
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device ath79_wmac_device = {
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.name = "ath9k",
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.id = -1,
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.resource = ath79_wmac_resources,
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.num_resources = ARRAY_SIZE(ath79_wmac_resources),
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.dev = {
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.platform_data = &ath79_wmac_data,
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},
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};
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static void __init ar913x_wmac_setup(void)
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{
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/* reset the WMAC */
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ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
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mdelay(10);
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ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
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mdelay(10);
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ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
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ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
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ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2;
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ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2;
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}
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static int ar933x_wmac_reset(void)
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{
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ath79_device_reset_set(AR933X_RESET_WMAC);
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ath79_device_reset_clear(AR933X_RESET_WMAC);
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return 0;
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}
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static int ar933x_r1_get_wmac_revision(void)
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{
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return ath79_soc_rev;
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}
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static void __init ar933x_wmac_setup(void)
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{
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u32 t;
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ar933x_wmac_reset();
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ath79_wmac_device.name = "ar933x_wmac";
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ath79_wmac_resources[0].start = AR933X_WMAC_BASE;
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ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1;
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ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2;
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ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2;
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t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
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if (t & AR933X_BOOTSTRAP_REF_CLK_40)
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ath79_wmac_data.is_clk_25mhz = false;
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else
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ath79_wmac_data.is_clk_25mhz = true;
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if (ath79_soc_rev == 1)
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ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
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ath79_wmac_data.external_reset = ar933x_wmac_reset;
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}
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static void ar934x_wmac_setup(void)
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{
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u32 t;
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ath79_wmac_device.name = "ar934x_wmac";
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ath79_wmac_resources[0].start = AR934X_WMAC_BASE;
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ath79_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1;
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ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
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ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
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t = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
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if (t & AR934X_BOOTSTRAP_REF_CLK_40)
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ath79_wmac_data.is_clk_25mhz = false;
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else
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ath79_wmac_data.is_clk_25mhz = true;
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}
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void __init ath79_register_wmac(u8 *cal_data)
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{
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if (soc_is_ar913x())
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ar913x_wmac_setup();
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else if (soc_is_ar933x())
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ar933x_wmac_setup();
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else if (soc_is_ar934x())
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ar934x_wmac_setup();
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else
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BUG();
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if (cal_data)
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memcpy(ath79_wmac_data.eeprom_data, cal_data,
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sizeof(ath79_wmac_data.eeprom_data));
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platform_device_register(&ath79_wmac_device);
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}
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