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301 lines
7.1 KiB
301 lines
7.1 KiB
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* SGI UV IRQ functions
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*
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* Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
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*/
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#include <linux/module.h>
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#include <linux/rbtree.h>
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#include <linux/irq.h>
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#include <asm/apic.h>
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#include <asm/uv/uv_irq.h>
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#include <asm/uv/uv_hub.h>
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/* MMR offset and pnode of hub sourcing interrupts for a given irq */
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struct uv_irq_2_mmr_pnode{
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struct rb_node list;
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unsigned long offset;
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int pnode;
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int irq;
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};
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static spinlock_t uv_irq_lock;
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static struct rb_root uv_irq_root;
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static int uv_set_irq_affinity(unsigned int, const struct cpumask *);
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static void uv_noop(unsigned int irq)
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{
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}
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static unsigned int uv_noop_ret(unsigned int irq)
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{
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return 0;
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}
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static void uv_ack_apic(unsigned int irq)
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{
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ack_APIC_irq();
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}
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struct irq_chip uv_irq_chip = {
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.name = "UV-CORE",
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.startup = uv_noop_ret,
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.shutdown = uv_noop,
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.enable = uv_noop,
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.disable = uv_noop,
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.ack = uv_noop,
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.mask = uv_noop,
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.unmask = uv_noop,
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.eoi = uv_ack_apic,
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.end = uv_noop,
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.set_affinity = uv_set_irq_affinity,
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};
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/*
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* Add offset and pnode information of the hub sourcing interrupts to the
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* rb tree for a specific irq.
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*/
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static int uv_set_irq_2_mmr_info(int irq, unsigned long offset, unsigned blade)
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{
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struct rb_node **link = &uv_irq_root.rb_node;
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struct rb_node *parent = NULL;
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struct uv_irq_2_mmr_pnode *n;
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struct uv_irq_2_mmr_pnode *e;
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unsigned long irqflags;
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n = kmalloc_node(sizeof(struct uv_irq_2_mmr_pnode), GFP_KERNEL,
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uv_blade_to_memory_nid(blade));
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if (!n)
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return -ENOMEM;
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n->irq = irq;
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n->offset = offset;
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n->pnode = uv_blade_to_pnode(blade);
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spin_lock_irqsave(&uv_irq_lock, irqflags);
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/* Find the right place in the rbtree: */
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while (*link) {
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parent = *link;
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e = rb_entry(parent, struct uv_irq_2_mmr_pnode, list);
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if (unlikely(irq == e->irq)) {
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/* irq entry exists */
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e->pnode = uv_blade_to_pnode(blade);
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e->offset = offset;
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spin_unlock_irqrestore(&uv_irq_lock, irqflags);
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kfree(n);
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return 0;
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}
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if (irq < e->irq)
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link = &(*link)->rb_left;
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else
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link = &(*link)->rb_right;
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}
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/* Insert the node into the rbtree. */
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rb_link_node(&n->list, parent, link);
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rb_insert_color(&n->list, &uv_irq_root);
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spin_unlock_irqrestore(&uv_irq_lock, irqflags);
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return 0;
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}
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/* Retrieve offset and pnode information from the rb tree for a specific irq */
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int uv_irq_2_mmr_info(int irq, unsigned long *offset, int *pnode)
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{
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struct uv_irq_2_mmr_pnode *e;
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struct rb_node *n;
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unsigned long irqflags;
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spin_lock_irqsave(&uv_irq_lock, irqflags);
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n = uv_irq_root.rb_node;
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while (n) {
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e = rb_entry(n, struct uv_irq_2_mmr_pnode, list);
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if (e->irq == irq) {
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*offset = e->offset;
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*pnode = e->pnode;
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spin_unlock_irqrestore(&uv_irq_lock, irqflags);
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return 0;
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}
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if (irq < e->irq)
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n = n->rb_left;
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else
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n = n->rb_right;
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}
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spin_unlock_irqrestore(&uv_irq_lock, irqflags);
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return -1;
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}
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/*
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* Re-target the irq to the specified CPU and enable the specified MMR located
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* on the specified blade to allow the sending of MSIs to the specified CPU.
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*/
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static int
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arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
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unsigned long mmr_offset, int restrict)
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{
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const struct cpumask *eligible_cpu = cpumask_of(cpu);
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struct irq_desc *desc = irq_to_desc(irq);
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struct irq_cfg *cfg;
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int mmr_pnode;
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unsigned long mmr_value;
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struct uv_IO_APIC_route_entry *entry;
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int err;
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BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) !=
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sizeof(unsigned long));
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cfg = irq_cfg(irq);
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err = assign_irq_vector(irq, cfg, eligible_cpu);
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if (err != 0)
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return err;
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if (restrict == UV_AFFINITY_CPU)
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desc->status |= IRQ_NO_BALANCING;
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else
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desc->status |= IRQ_MOVE_PCNTXT;
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set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
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irq_name);
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mmr_value = 0;
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entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
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entry->vector = cfg->vector;
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entry->delivery_mode = apic->irq_delivery_mode;
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entry->dest_mode = apic->irq_dest_mode;
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entry->polarity = 0;
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entry->trigger = 0;
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entry->mask = 0;
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entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
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mmr_pnode = uv_blade_to_pnode(mmr_blade);
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uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
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if (cfg->move_in_progress)
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send_cleanup_vector(cfg);
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return irq;
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}
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/*
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* Disable the specified MMR located on the specified blade so that MSIs are
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* longer allowed to be sent.
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*/
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static void arch_disable_uv_irq(int mmr_pnode, unsigned long mmr_offset)
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{
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unsigned long mmr_value;
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struct uv_IO_APIC_route_entry *entry;
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BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) !=
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sizeof(unsigned long));
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mmr_value = 0;
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entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
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entry->mask = 1;
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uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
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}
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static int uv_set_irq_affinity(unsigned int irq, const struct cpumask *mask)
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{
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struct irq_desc *desc = irq_to_desc(irq);
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struct irq_cfg *cfg = desc->chip_data;
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unsigned int dest;
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unsigned long mmr_value;
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struct uv_IO_APIC_route_entry *entry;
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unsigned long mmr_offset;
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unsigned mmr_pnode;
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if (set_desc_affinity(desc, mask, &dest))
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return -1;
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mmr_value = 0;
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entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
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entry->vector = cfg->vector;
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entry->delivery_mode = apic->irq_delivery_mode;
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entry->dest_mode = apic->irq_dest_mode;
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entry->polarity = 0;
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entry->trigger = 0;
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entry->mask = 0;
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entry->dest = dest;
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/* Get previously stored MMR and pnode of hub sourcing interrupts */
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if (uv_irq_2_mmr_info(irq, &mmr_offset, &mmr_pnode))
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return -1;
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uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
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if (cfg->move_in_progress)
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send_cleanup_vector(cfg);
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return 0;
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}
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/*
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* Set up a mapping of an available irq and vector, and enable the specified
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* MMR that defines the MSI that is to be sent to the specified CPU when an
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* interrupt is raised.
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*/
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int uv_setup_irq(char *irq_name, int cpu, int mmr_blade,
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unsigned long mmr_offset, int restrict)
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{
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int irq, ret;
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irq = create_irq_nr(NR_IRQS_LEGACY, uv_blade_to_memory_nid(mmr_blade));
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if (irq <= 0)
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return -EBUSY;
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ret = arch_enable_uv_irq(irq_name, irq, cpu, mmr_blade, mmr_offset,
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restrict);
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if (ret == irq)
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uv_set_irq_2_mmr_info(irq, mmr_offset, mmr_blade);
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else
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destroy_irq(irq);
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return ret;
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}
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EXPORT_SYMBOL_GPL(uv_setup_irq);
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/*
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* Tear down a mapping of an irq and vector, and disable the specified MMR that
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* defined the MSI that was to be sent to the specified CPU when an interrupt
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* was raised.
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*
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* Set mmr_blade and mmr_offset to what was passed in on uv_setup_irq().
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*/
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void uv_teardown_irq(unsigned int irq)
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{
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struct uv_irq_2_mmr_pnode *e;
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struct rb_node *n;
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unsigned long irqflags;
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spin_lock_irqsave(&uv_irq_lock, irqflags);
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n = uv_irq_root.rb_node;
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while (n) {
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e = rb_entry(n, struct uv_irq_2_mmr_pnode, list);
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if (e->irq == irq) {
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arch_disable_uv_irq(e->pnode, e->offset);
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rb_erase(n, &uv_irq_root);
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kfree(e);
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break;
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}
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if (irq < e->irq)
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n = n->rb_left;
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else
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n = n->rb_right;
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}
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spin_unlock_irqrestore(&uv_irq_lock, irqflags);
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destroy_irq(irq);
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}
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EXPORT_SYMBOL_GPL(uv_teardown_irq);
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