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252 lines
9.2 KiB
252 lines
9.2 KiB
/* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
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*
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* Copyright 2009 Samsung Electronics Co.
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* Byungho Min <bhmin@samsung.com>
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*
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* S5PC1XX clock register definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __PLAT_REGS_CLOCK_H
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#define __PLAT_REGS_CLOCK_H __FILE__
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#define S5PC100_CLKREG(x) (S5PC1XX_VA_CLK + (x))
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#define S5PC100_CLKREG_OTHER(x) (S5PC1XX_VA_CLK_OTHER + (x))
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/* s5pc100 register for clock */
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#define S5PC100_APLL_LOCK S5PC100_CLKREG(0x00)
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#define S5PC100_MPLL_LOCK S5PC100_CLKREG(0x04)
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#define S5PC100_EPLL_LOCK S5PC100_CLKREG(0x08)
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#define S5PC100_HPLL_LOCK S5PC100_CLKREG(0x0C)
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#define S5PC100_APLL_CON S5PC100_CLKREG(0x100)
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#define S5PC100_MPLL_CON S5PC100_CLKREG(0x104)
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#define S5PC100_EPLL_CON S5PC100_CLKREG(0x108)
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#define S5PC100_HPLL_CON S5PC100_CLKREG(0x10C)
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#define S5PC100_CLKSRC0 S5PC100_CLKREG(0x200)
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#define S5PC100_CLKSRC1 S5PC100_CLKREG(0x204)
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#define S5PC100_CLKSRC2 S5PC100_CLKREG(0x208)
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#define S5PC100_CLKSRC3 S5PC100_CLKREG(0x20C)
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#define S5PC100_CLKDIV0 S5PC100_CLKREG(0x300)
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#define S5PC100_CLKDIV1 S5PC100_CLKREG(0x304)
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#define S5PC100_CLKDIV2 S5PC100_CLKREG(0x308)
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#define S5PC100_CLKDIV3 S5PC100_CLKREG(0x30C)
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#define S5PC100_CLKDIV4 S5PC100_CLKREG(0x310)
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#define S5PC100_CLK_OUT S5PC100_CLKREG(0x400)
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#define S5PC100_CLKGATE_D00 S5PC100_CLKREG(0x500)
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#define S5PC100_CLKGATE_D01 S5PC100_CLKREG(0x504)
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#define S5PC100_CLKGATE_D02 S5PC100_CLKREG(0x508)
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#define S5PC100_CLKGATE_D10 S5PC100_CLKREG(0x520)
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#define S5PC100_CLKGATE_D11 S5PC100_CLKREG(0x524)
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#define S5PC100_CLKGATE_D12 S5PC100_CLKREG(0x528)
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#define S5PC100_CLKGATE_D13 S5PC100_CLKREG(0x52C)
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#define S5PC100_CLKGATE_D14 S5PC100_CLKREG(0x530)
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#define S5PC100_CLKGATE_D15 S5PC100_CLKREG(0x534)
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#define S5PC100_CLKGATE_D20 S5PC100_CLKREG(0x540)
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#define S5PC100_SCLKGATE0 S5PC100_CLKREG(0x560)
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#define S5PC100_SCLKGATE1 S5PC100_CLKREG(0x564)
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/* EPLL_CON */
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#define S5PC100_EPLL_EN (1<<31)
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#define S5PC100_EPLL_MASK 0xffffffff
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#define S5PC100_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s)))
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/* CLKSRC0..CLKSRC3 -> mostly removed due to clksrc updates */
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#define S5PC100_CLKSRC1_CLK48M_MASK (0x1<<24)
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#define S5PC100_CLKSRC1_CLK48M_SHIFT (24)
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/* CLKDIV0 */
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#define S5PC100_CLKDIV0_APLL_MASK (0x1<<0)
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#define S5PC100_CLKDIV0_APLL_SHIFT (0)
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#define S5PC100_CLKDIV0_ARM_MASK (0x7<<4)
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#define S5PC100_CLKDIV0_ARM_SHIFT (4)
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#define S5PC100_CLKDIV0_D0_MASK (0x7<<8)
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#define S5PC100_CLKDIV0_D0_SHIFT (8)
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#define S5PC100_CLKDIV0_PCLKD0_MASK (0x7<<12)
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#define S5PC100_CLKDIV0_PCLKD0_SHIFT (12)
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#define S5PC100_CLKDIV0_SECSS_MASK (0x7<<16)
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#define S5PC100_CLKDIV0_SECSS_SHIFT (16)
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/* CLKDIV1 (OneNAND clock only used in one place, removed) */
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#define S5PC100_CLKDIV1_APLL2_MASK (0x7<<0)
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#define S5PC100_CLKDIV1_APLL2_SHIFT (0)
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#define S5PC100_CLKDIV1_MPLL_MASK (0x3<<4)
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#define S5PC100_CLKDIV1_MPLL_SHIFT (4)
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#define S5PC100_CLKDIV1_MPLL2_MASK (0x1<<8)
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#define S5PC100_CLKDIV1_MPLL2_SHIFT (8)
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#define S5PC100_CLKDIV1_D1_MASK (0x7<<12)
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#define S5PC100_CLKDIV1_D1_SHIFT (12)
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#define S5PC100_CLKDIV1_PCLKD1_MASK (0x7<<16)
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#define S5PC100_CLKDIV1_PCLKD1_SHIFT (16)
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#define S5PC100_CLKDIV1_CAM_MASK (0x1F<<24)
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#define S5PC100_CLKDIV1_CAM_SHIFT (24)
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/* CLKDIV2 => removed in clksrc update */
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/* CLKDIV3 => removed in clksrc update, or not needed */
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/* CLKDIV4 => removed in clksrc update, or not needed */
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/* HCLKD0/PCLKD0 Clock Gate 0 Registers */
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#define S5PC100_CLKGATE_D00_INTC (1<<0)
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#define S5PC100_CLKGATE_D00_TZIC (1<<1)
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#define S5PC100_CLKGATE_D00_CFCON (1<<2)
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#define S5PC100_CLKGATE_D00_MDMA (1<<3)
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#define S5PC100_CLKGATE_D00_G2D (1<<4)
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#define S5PC100_CLKGATE_D00_SECSS (1<<5)
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#define S5PC100_CLKGATE_D00_CSSYS (1<<6)
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/* HCLKD0/PCLKD0 Clock Gate 1 Registers */
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#define S5PC100_CLKGATE_D01_DMC (1<<0)
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#define S5PC100_CLKGATE_D01_SROMC (1<<1)
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#define S5PC100_CLKGATE_D01_ONENAND (1<<2)
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#define S5PC100_CLKGATE_D01_NFCON (1<<3)
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#define S5PC100_CLKGATE_D01_INTMEM (1<<4)
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#define S5PC100_CLKGATE_D01_EBI (1<<5)
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/* PCLKD0 Clock Gate 2 Registers */
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#define S5PC100_CLKGATE_D02_SECKEY (1<<1)
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#define S5PC100_CLKGATE_D02_SDM (1<<2)
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/* HCLKD1/PCLKD1 Clock Gate 0 Registers */
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#define S5PC100_CLKGATE_D10_PDMA0 (1<<0)
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#define S5PC100_CLKGATE_D10_PDMA1 (1<<1)
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#define S5PC100_CLKGATE_D10_USBHOST (1<<2)
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#define S5PC100_CLKGATE_D10_USBOTG (1<<3)
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#define S5PC100_CLKGATE_D10_MODEMIF (1<<4)
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#define S5PC100_CLKGATE_D10_HSMMC0 (1<<5)
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#define S5PC100_CLKGATE_D10_HSMMC1 (1<<6)
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#define S5PC100_CLKGATE_D10_HSMMC2 (1<<7)
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/* HCLKD1/PCLKD1 Clock Gate 1 Registers */
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#define S5PC100_CLKGATE_D11_LCD (1<<0)
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#define S5PC100_CLKGATE_D11_ROTATOR (1<<1)
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#define S5PC100_CLKGATE_D11_FIMC0 (1<<2)
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#define S5PC100_CLKGATE_D11_FIMC1 (1<<3)
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#define S5PC100_CLKGATE_D11_FIMC2 (1<<4)
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#define S5PC100_CLKGATE_D11_JPEG (1<<5)
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#define S5PC100_CLKGATE_D11_DSI (1<<6)
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#define S5PC100_CLKGATE_D11_CSI (1<<7)
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#define S5PC100_CLKGATE_D11_G3D (1<<8)
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/* HCLKD1/PCLKD1 Clock Gate 2 Registers */
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#define S5PC100_CLKGATE_D12_TV (1<<0)
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#define S5PC100_CLKGATE_D12_VP (1<<1)
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#define S5PC100_CLKGATE_D12_MIXER (1<<2)
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#define S5PC100_CLKGATE_D12_HDMI (1<<3)
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#define S5PC100_CLKGATE_D12_MFC (1<<4)
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/* HCLKD1/PCLKD1 Clock Gate 3 Registers */
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#define S5PC100_CLKGATE_D13_CHIPID (1<<0)
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#define S5PC100_CLKGATE_D13_GPIO (1<<1)
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#define S5PC100_CLKGATE_D13_APC (1<<2)
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#define S5PC100_CLKGATE_D13_IEC (1<<3)
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#define S5PC100_CLKGATE_D13_PWM (1<<6)
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#define S5PC100_CLKGATE_D13_SYSTIMER (1<<7)
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#define S5PC100_CLKGATE_D13_WDT (1<<8)
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#define S5PC100_CLKGATE_D13_RTC (1<<9)
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/* HCLKD1/PCLKD1 Clock Gate 4 Registers */
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#define S5PC100_CLKGATE_D14_UART0 (1<<0)
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#define S5PC100_CLKGATE_D14_UART1 (1<<1)
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#define S5PC100_CLKGATE_D14_UART2 (1<<2)
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#define S5PC100_CLKGATE_D14_UART3 (1<<3)
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#define S5PC100_CLKGATE_D14_IIC (1<<4)
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#define S5PC100_CLKGATE_D14_HDMI_IIC (1<<5)
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#define S5PC100_CLKGATE_D14_SPI0 (1<<6)
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#define S5PC100_CLKGATE_D14_SPI1 (1<<7)
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#define S5PC100_CLKGATE_D14_SPI2 (1<<8)
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#define S5PC100_CLKGATE_D14_IRDA (1<<9)
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#define S5PC100_CLKGATE_D14_CCAN0 (1<<10)
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#define S5PC100_CLKGATE_D14_CCAN1 (1<<11)
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#define S5PC100_CLKGATE_D14_HSITX (1<<12)
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#define S5PC100_CLKGATE_D14_HSIRX (1<<13)
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/* HCLKD1/PCLKD1 Clock Gate 5 Registers */
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#define S5PC100_CLKGATE_D15_IIS0 (1<<0)
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#define S5PC100_CLKGATE_D15_IIS1 (1<<1)
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#define S5PC100_CLKGATE_D15_IIS2 (1<<2)
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#define S5PC100_CLKGATE_D15_AC97 (1<<3)
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#define S5PC100_CLKGATE_D15_PCM0 (1<<4)
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#define S5PC100_CLKGATE_D15_PCM1 (1<<5)
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#define S5PC100_CLKGATE_D15_SPDIF (1<<6)
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#define S5PC100_CLKGATE_D15_TSADC (1<<7)
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#define S5PC100_CLKGATE_D15_KEYIF (1<<8)
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#define S5PC100_CLKGATE_D15_CG (1<<9)
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/* HCLKD2 Clock Gate 0 Registers */
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#define S5PC100_CLKGATE_D20_HCLKD2 (1<<0)
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#define S5PC100_CLKGATE_D20_I2SD2 (1<<1)
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/* Special Clock Gate 0 Registers */
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#define S5PC100_CLKGATE_SCLK0_HPM (1<<0)
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#define S5PC100_CLKGATE_SCLK0_PWI (1<<1)
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#define S5PC100_CLKGATE_SCLK0_ONENAND (1<<2)
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#define S5PC100_CLKGATE_SCLK0_UART (1<<3)
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#define S5PC100_CLKGATE_SCLK0_SPI0 (1<<4)
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#define S5PC100_CLKGATE_SCLK0_SPI1 (1<<5)
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#define S5PC100_CLKGATE_SCLK0_SPI2 (1<<6)
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#define S5PC100_CLKGATE_SCLK0_SPI0_48 (1<<7)
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#define S5PC100_CLKGATE_SCLK0_SPI1_48 (1<<8)
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#define S5PC100_CLKGATE_SCLK0_SPI2_48 (1<<9)
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#define S5PC100_CLKGATE_SCLK0_IRDA (1<<10)
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#define S5PC100_CLKGATE_SCLK0_USBHOST (1<<11)
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#define S5PC100_CLKGATE_SCLK0_MMC0 (1<<12)
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#define S5PC100_CLKGATE_SCLK0_MMC1 (1<<13)
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#define S5PC100_CLKGATE_SCLK0_MMC2 (1<<14)
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#define S5PC100_CLKGATE_SCLK0_MMC0_48 (1<<15)
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#define S5PC100_CLKGATE_SCLK0_MMC1_48 (1<<16)
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#define S5PC100_CLKGATE_SCLK0_MMC2_48 (1<<17)
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/* Special Clock Gate 1 Registers */
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#define S5PC100_CLKGATE_SCLK1_LCD (1<<0)
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#define S5PC100_CLKGATE_SCLK1_FIMC0 (1<<1)
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#define S5PC100_CLKGATE_SCLK1_FIMC1 (1<<2)
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#define S5PC100_CLKGATE_SCLK1_FIMC2 (1<<3)
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#define S5PC100_CLKGATE_SCLK1_TV54 (1<<4)
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#define S5PC100_CLKGATE_SCLK1_VDAC54 (1<<5)
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#define S5PC100_CLKGATE_SCLK1_MIXER (1<<6)
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#define S5PC100_CLKGATE_SCLK1_HDMI (1<<7)
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#define S5PC100_CLKGATE_SCLK1_AUDIO0 (1<<8)
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#define S5PC100_CLKGATE_SCLK1_AUDIO1 (1<<9)
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#define S5PC100_CLKGATE_SCLK1_AUDIO2 (1<<10)
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#define S5PC100_CLKGATE_SCLK1_SPDIF (1<<11)
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#define S5PC100_CLKGATE_SCLK1_CAM (1<<12)
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#define S5PC100_SWRESET S5PC100_CLKREG_OTHER(0x000)
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#define S5PC100_OND_SWRESET S5PC100_CLKREG_OTHER(0x008)
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#define S5PC100_GEN_CTRL S5PC100_CLKREG_OTHER(0x100)
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#define S5PC100_GEN_STATUS S5PC100_CLKREG_OTHER(0x104)
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#define S5PC100_MEM_SYS_CFG S5PC100_CLKREG_OTHER(0x200)
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#define S5PC100_CAM_MUX_SEL S5PC100_CLKREG_OTHER(0x300)
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#define S5PC100_MIXER_OUT_SEL S5PC100_CLKREG_OTHER(0x304)
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#define S5PC100_LPMP_MODE_SEL S5PC100_CLKREG_OTHER(0x308)
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#define S5PC100_MIPI_PHY_CON0 S5PC100_CLKREG_OTHER(0x400)
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#define S5PC100_MIPI_PHY_CON1 S5PC100_CLKREG_OTHER(0x414)
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#define S5PC100_HDMI_PHY_CON0 S5PC100_CLKREG_OTHER(0x420)
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#define S5PC100_SWRESET_RESETVAL 0xc100
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#define S5PC100_OTHER_SYS_INT 24
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#define S5PC100_OTHER_STA_TYPE 23
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#define STA_TYPE_EXPON 0
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#define STA_TYPE_SFR 1
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#define S5PC100_SLEEP_CFG_OSC_EN 0
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/* OTHERS Resgister */
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#define S5PC100_OTHERS_USB_SIG_MASK (1 << 16)
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#define S5PC100_OTHERS_MIPI_DPHY_EN (1 << 28)
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/* MIPI D-PHY Control Register 0 */
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#define S5PC100_MIPI_PHY_CON0_M_RESETN (1 << 1)
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#define S5PC100_MIPI_PHY_CON0_S_RESETN (1 << 0)
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#endif /* _PLAT_REGS_CLOCK_H */
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