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267 lines
8.6 KiB
267 lines
8.6 KiB
/*
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* ibm_emac.h
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*
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*
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* Armin Kuster akuster@mvista.com
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* June, 2002
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*
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* Copyright 2002 MontaVista Softare Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef _IBM_EMAC_H_
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#define _IBM_EMAC_H_
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/* General defines needed for the driver */
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/* Emac */
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typedef struct emac_regs {
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u32 em0mr0;
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u32 em0mr1;
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u32 em0tmr0;
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u32 em0tmr1;
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u32 em0rmr;
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u32 em0isr;
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u32 em0iser;
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u32 em0iahr;
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u32 em0ialr;
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u32 em0vtpid;
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u32 em0vtci;
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u32 em0ptr;
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u32 em0iaht1;
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u32 em0iaht2;
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u32 em0iaht3;
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u32 em0iaht4;
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u32 em0gaht1;
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u32 em0gaht2;
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u32 em0gaht3;
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u32 em0gaht4;
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u32 em0lsah;
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u32 em0lsal;
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u32 em0ipgvr;
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u32 em0stacr;
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u32 em0trtr;
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u32 em0rwmr;
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} emac_t;
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/* MODE REG 0 */
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#define EMAC_M0_RXI 0x80000000
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#define EMAC_M0_TXI 0x40000000
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#define EMAC_M0_SRST 0x20000000
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#define EMAC_M0_TXE 0x10000000
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#define EMAC_M0_RXE 0x08000000
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#define EMAC_M0_WKE 0x04000000
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/* MODE Reg 1 */
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#define EMAC_M1_FDE 0x80000000
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#define EMAC_M1_ILE 0x40000000
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#define EMAC_M1_VLE 0x20000000
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#define EMAC_M1_EIFC 0x10000000
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#define EMAC_M1_APP 0x08000000
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#define EMAC_M1_AEMI 0x02000000
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#define EMAC_M1_IST 0x01000000
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#define EMAC_M1_MF_1000GPCS 0x00c00000 /* Internal GPCS */
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#define EMAC_M1_MF_1000MBPS 0x00800000 /* External GPCS */
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#define EMAC_M1_MF_100MBPS 0x00400000
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#define EMAC_M1_RFS_16K 0x00280000 /* 000 for 512 byte */
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#define EMAC_M1_TR 0x00008000
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#ifdef CONFIG_IBM_EMAC4
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#define EMAC_M1_RFS_8K 0x00200000
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#define EMAC_M1_RFS_4K 0x00180000
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#define EMAC_M1_RFS_2K 0x00100000
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#define EMAC_M1_RFS_1K 0x00080000
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#define EMAC_M1_TX_FIFO_16K 0x00050000 /* 0's for 512 byte */
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#define EMAC_M1_TX_FIFO_8K 0x00040000
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#define EMAC_M1_TX_FIFO_4K 0x00030000
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#define EMAC_M1_TX_FIFO_2K 0x00020000
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#define EMAC_M1_TX_FIFO_1K 0x00010000
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#define EMAC_M1_TX_TR 0x00008000
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#define EMAC_M1_TX_MWSW 0x00001000 /* 0 wait for status */
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#define EMAC_M1_JUMBO_ENABLE 0x00000800 /* Upt to 9Kr status */
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#define EMAC_M1_OPB_CLK_66 0x00000008 /* 66Mhz */
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#define EMAC_M1_OPB_CLK_83 0x00000010 /* 83Mhz */
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#define EMAC_M1_OPB_CLK_100 0x00000018 /* 100Mhz */
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#define EMAC_M1_OPB_CLK_100P 0x00000020 /* 100Mhz+ */
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#else /* CONFIG_IBM_EMAC4 */
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#define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */
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#define EMAC_M1_RFS_2K 0x00200000
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#define EMAC_M1_RFS_1K 0x00100000
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#define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */
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#define EMAC_M1_TX_FIFO_1K 0x00040000
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#define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
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#define EMAC_M1_TR1_DEPEND 0x00004000
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#define EMAC_M1_TR1_MULTI 0x00002000
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#define EMAC_M1_JUMBO_ENABLE 0x00001000
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#endif /* CONFIG_IBM_EMAC4 */
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#define EMAC_M1_BASE (EMAC_M1_TX_FIFO_2K | \
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EMAC_M1_APP | \
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EMAC_M1_TR | EMAC_M1_VLE)
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/* Transmit Mode Register 0 */
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#define EMAC_TMR0_GNP0 0x80000000
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#define EMAC_TMR0_GNP1 0x40000000
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#define EMAC_TMR0_GNPD 0x20000000
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#define EMAC_TMR0_FC 0x10000000
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#define EMAC_TMR0_TFAE_2_32 0x00000001
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#define EMAC_TMR0_TFAE_4_64 0x00000002
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#define EMAC_TMR0_TFAE_8_128 0x00000003
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#define EMAC_TMR0_TFAE_16_256 0x00000004
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#define EMAC_TMR0_TFAE_32_512 0x00000005
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#define EMAC_TMR0_TFAE_64_1024 0x00000006
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#define EMAC_TMR0_TFAE_128_2048 0x00000007
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/* Receive Mode Register */
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#define EMAC_RMR_SP 0x80000000
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#define EMAC_RMR_SFCS 0x40000000
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#define EMAC_RMR_ARRP 0x20000000
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#define EMAC_RMR_ARP 0x10000000
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#define EMAC_RMR_AROP 0x08000000
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#define EMAC_RMR_ARPI 0x04000000
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#define EMAC_RMR_PPP 0x02000000
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#define EMAC_RMR_PME 0x01000000
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#define EMAC_RMR_PMME 0x00800000
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#define EMAC_RMR_IAE 0x00400000
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#define EMAC_RMR_MIAE 0x00200000
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#define EMAC_RMR_BAE 0x00100000
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#define EMAC_RMR_MAE 0x00080000
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#define EMAC_RMR_RFAF_2_32 0x00000001
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#define EMAC_RMR_RFAF_4_64 0x00000002
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#define EMAC_RMR_RFAF_8_128 0x00000003
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#define EMAC_RMR_RFAF_16_256 0x00000004
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#define EMAC_RMR_RFAF_32_512 0x00000005
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#define EMAC_RMR_RFAF_64_1024 0x00000006
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#define EMAC_RMR_RFAF_128_2048 0x00000007
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#define EMAC_RMR_BASE (EMAC_RMR_IAE | EMAC_RMR_BAE)
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/* Interrupt Status & enable Regs */
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#define EMAC_ISR_OVR 0x02000000
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#define EMAC_ISR_PP 0x01000000
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#define EMAC_ISR_BP 0x00800000
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#define EMAC_ISR_RP 0x00400000
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#define EMAC_ISR_SE 0x00200000
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#define EMAC_ISR_ALE 0x00100000
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#define EMAC_ISR_BFCS 0x00080000
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#define EMAC_ISR_PTLE 0x00040000
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#define EMAC_ISR_ORE 0x00020000
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#define EMAC_ISR_IRE 0x00010000
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#define EMAC_ISR_DBDM 0x00000200
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#define EMAC_ISR_DB0 0x00000100
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#define EMAC_ISR_SE0 0x00000080
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#define EMAC_ISR_TE0 0x00000040
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#define EMAC_ISR_DB1 0x00000020
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#define EMAC_ISR_SE1 0x00000010
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#define EMAC_ISR_TE1 0x00000008
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#define EMAC_ISR_MOS 0x00000002
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#define EMAC_ISR_MOF 0x00000001
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/* STA CONTROL REG */
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#define EMAC_STACR_OC 0x00008000
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#define EMAC_STACR_PHYE 0x00004000
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#define EMAC_STACR_WRITE 0x00002000
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#define EMAC_STACR_READ 0x00001000
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#define EMAC_STACR_CLK_83MHZ 0x00000800 /* 0's for 50Mhz */
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#define EMAC_STACR_CLK_66MHZ 0x00000400
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#define EMAC_STACR_CLK_100MHZ 0x00000C00
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/* Transmit Request Threshold Register */
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#define EMAC_TRTR_1600 0x18000000 /* 0's for 64 Bytes */
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#define EMAC_TRTR_1024 0x0f000000
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#define EMAC_TRTR_512 0x07000000
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#define EMAC_TRTR_256 0x03000000
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#define EMAC_TRTR_192 0x10000000
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#define EMAC_TRTR_128 0x01000000
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#define EMAC_TX_CTRL_GFCS 0x0200
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#define EMAC_TX_CTRL_GP 0x0100
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#define EMAC_TX_CTRL_ISA 0x0080
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#define EMAC_TX_CTRL_RSA 0x0040
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#define EMAC_TX_CTRL_IVT 0x0020
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#define EMAC_TX_CTRL_RVT 0x0010
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#define EMAC_TX_CTRL_TAH_CSUM 0x000e /* TAH only */
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#define EMAC_TX_CTRL_TAH_SEG4 0x000a /* TAH only */
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#define EMAC_TX_CTRL_TAH_SEG3 0x0008 /* TAH only */
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#define EMAC_TX_CTRL_TAH_SEG2 0x0006 /* TAH only */
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#define EMAC_TX_CTRL_TAH_SEG1 0x0004 /* TAH only */
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#define EMAC_TX_CTRL_TAH_SEG0 0x0002 /* TAH only */
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#define EMAC_TX_CTRL_TAH_DIS 0x0000 /* TAH only */
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#define EMAC_TX_CTRL_DFLT ( \
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MAL_TX_CTRL_INTR | EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP )
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/* madmal transmit status / Control bits */
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#define EMAC_TX_ST_BFCS 0x0200
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#define EMAC_TX_ST_BPP 0x0100
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#define EMAC_TX_ST_LCS 0x0080
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#define EMAC_TX_ST_ED 0x0040
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#define EMAC_TX_ST_EC 0x0020
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#define EMAC_TX_ST_LC 0x0010
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#define EMAC_TX_ST_MC 0x0008
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#define EMAC_TX_ST_SC 0x0004
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#define EMAC_TX_ST_UR 0x0002
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#define EMAC_TX_ST_SQE 0x0001
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/* madmal receive status / Control bits */
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#define EMAC_RX_ST_OE 0x0200
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#define EMAC_RX_ST_PP 0x0100
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#define EMAC_RX_ST_BP 0x0080
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#define EMAC_RX_ST_RP 0x0040
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#define EMAC_RX_ST_SE 0x0020
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#define EMAC_RX_ST_AE 0x0010
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#define EMAC_RX_ST_BFCS 0x0008
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#define EMAC_RX_ST_PTL 0x0004
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#define EMAC_RX_ST_ORE 0x0002
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#define EMAC_RX_ST_IRE 0x0001
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#define EMAC_BAD_RX_PACKET 0x02ff
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#define EMAC_CSUM_VER_ERROR 0x0003
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/* identify a bad rx packet dependent on emac features */
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#ifdef CONFIG_IBM_EMAC4
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#define EMAC_IS_BAD_RX_PACKET(desc) \
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(((desc & (EMAC_BAD_RX_PACKET & ~EMAC_CSUM_VER_ERROR)) || \
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((desc & EMAC_CSUM_VER_ERROR) == EMAC_RX_ST_ORE) || \
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((desc & EMAC_CSUM_VER_ERROR) == EMAC_RX_ST_IRE)))
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#else
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#define EMAC_IS_BAD_RX_PACKET(desc) \
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(desc & EMAC_BAD_RX_PACKET)
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#endif
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/* SoC implementation specific EMAC register defaults */
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#if defined(CONFIG_440GP)
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#define EMAC_RWMR_DEFAULT 0x80009000
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#define EMAC_TMR0_DEFAULT 0x00000000
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#define EMAC_TMR1_DEFAULT 0xf8640000
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#elif defined(CONFIG_440GX)
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#define EMAC_RWMR_DEFAULT 0x1000a200
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#define EMAC_TMR0_DEFAULT EMAC_TMR0_TFAE_2_32
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#define EMAC_TMR1_DEFAULT 0xa00f0000
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#elif defined(CONFIG_440SP)
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#define EMAC_RWMR_DEFAULT 0x08002000
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#define EMAC_TMR0_DEFAULT EMAC_TMR0_TFAE_128_2048
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#define EMAC_TMR1_DEFAULT 0xf8200000
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#else
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#define EMAC_RWMR_DEFAULT 0x0f002000
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#define EMAC_TMR0_DEFAULT 0x00000000
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#define EMAC_TMR1_DEFAULT 0x380f0000
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#endif /* CONFIG_440GP */
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/* Revision specific EMAC register defaults */
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#ifdef CONFIG_IBM_EMAC4
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#define EMAC_M1_DEFAULT (EMAC_M1_BASE | \
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EMAC_M1_OPB_CLK_83 | \
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EMAC_M1_TX_MWSW)
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#define EMAC_RMR_DEFAULT (EMAC_RMR_BASE | \
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EMAC_RMR_RFAF_128_2048)
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#define EMAC_TMR0_XMIT (EMAC_TMR0_GNP0 | \
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EMAC_TMR0_DEFAULT)
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#define EMAC_TRTR_DEFAULT EMAC_TRTR_1024
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#else /* !CONFIG_IBM_EMAC4 */
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#define EMAC_M1_DEFAULT EMAC_M1_BASE
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#define EMAC_RMR_DEFAULT EMAC_RMR_BASE
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#define EMAC_TMR0_XMIT EMAC_TMR0_GNP0
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#define EMAC_TRTR_DEFAULT EMAC_TRTR_1600
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#endif /* CONFIG_IBM_EMAC4 */
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#endif
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