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274 lines
7.5 KiB
274 lines
7.5 KiB
/* Stand alone funtions for QSpan Tundra support.
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <asm/mpc8xx.h>
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extern void puthex(unsigned long val);
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extern void puts(const char *);
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/* To map PCI devices, you first write 0xffffffff into the device
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* base address registers. When the register is read back, the
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* number of most significant '1' bits describes the amount of address
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* space needed for mapping. If the most significant bit is not set,
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* either the device does not use that address register, or it has
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* a fixed address that we can't change. After the address is assigned,
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* the command register has to be written to enable the card.
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*/
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typedef struct {
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u_char pci_bus;
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u_char pci_devfn;
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ushort pci_command;
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uint pci_addrs[6];
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} pci_map_t;
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/* We should probably dynamically allocate these structures.
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*/
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#define MAX_PCI_DEVS 32
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int pci_dev_cnt;
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pci_map_t pci_map[MAX_PCI_DEVS];
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void pci_conf_write(int bus, int device, int func, int reg, uint writeval);
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void pci_conf_read(int bus, int device, int func, int reg, void *readval);
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void probe_addresses(int bus, int devfn);
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void map_pci_addrs(void);
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extern int
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qs_pci_read_config_byte(unsigned char bus, unsigned char dev_fn,
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unsigned char offset, unsigned char *val);
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extern int
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qs_pci_read_config_word(unsigned char bus, unsigned char dev_fn,
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unsigned char offset, unsigned short *val);
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extern int
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qs_pci_read_config_dword(unsigned char bus, unsigned char dev_fn,
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unsigned char offset, unsigned int *val);
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extern int
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qs_pci_write_config_byte(unsigned char bus, unsigned char dev_fn,
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unsigned char offset, unsigned char val);
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extern int
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qs_pci_write_config_word(unsigned char bus, unsigned char dev_fn,
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unsigned char offset, unsigned short val);
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extern int
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qs_pci_write_config_dword(unsigned char bus, unsigned char dev_fn,
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unsigned char offset, unsigned int val);
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/* This is a really stripped version of PCI bus scan. All we are
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* looking for are devices that exist.
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*/
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void
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pci_scanner(int addr_probe)
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{
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unsigned int devfn, l, class, bus_number;
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unsigned char hdr_type, is_multi;
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is_multi = 0;
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bus_number = 0;
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for (devfn = 0; devfn < 0xff; ++devfn) {
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/* The device numbers are comprised of upper 5 bits of
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* device number and lower 3 bits of multi-function number.
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*/
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if ((devfn & 7) && !is_multi) {
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/* Don't scan multifunction addresses if this is
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* not a multifunction device.
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*/
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continue;
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}
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/* Read the header to determine card type.
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*/
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qs_pci_read_config_byte(bus_number, devfn, PCI_HEADER_TYPE,
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&hdr_type);
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/* If this is a base device number, check the header to
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* determine if it is mulifunction.
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*/
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if ((devfn & 7) == 0)
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is_multi = hdr_type & 0x80;
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/* Check to see if the board is really in the slot.
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*/
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qs_pci_read_config_dword(bus_number, devfn, PCI_VENDOR_ID, &l);
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/* some broken boards return 0 if a slot is empty: */
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if (l == 0xffffffff || l == 0x00000000 || l == 0x0000ffff ||
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l == 0xffff0000) {
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/* Nothing there.
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*/
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is_multi = 0;
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continue;
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}
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/* If we are not performing an address probe,
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* just simply print out some information.
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*/
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if (!addr_probe) {
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qs_pci_read_config_dword(bus_number, devfn,
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PCI_CLASS_REVISION, &class);
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class >>= 8; /* upper 3 bytes */
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#if 0
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printf("Found (%3d:%d): vendor 0x%04x, device 0x%04x, class 0x%06x\n",
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(devfn >> 3), (devfn & 7),
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(l & 0xffff), (l >> 16) & 0xffff, class);
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#else
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puts("Found ("); puthex(devfn >> 3);
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puts(":"); puthex(devfn & 7);
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puts("): vendor "); puthex(l & 0xffff);
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puts(", device "); puthex((l >> 16) & 0xffff);
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puts(", class "); puthex(class); puts("\n");
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#endif
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}
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else {
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/* If this is a "normal" device, build address list.
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*/
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if ((hdr_type & 0x7f) == PCI_HEADER_TYPE_NORMAL)
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probe_addresses(bus_number, devfn);
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}
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}
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/* Now map the boards.
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*/
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if (addr_probe)
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map_pci_addrs();
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}
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/* Probe addresses for the specified device. This is a destructive
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* operation because it writes the registers.
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*/
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void
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probe_addresses(bus, devfn)
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{
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int i;
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uint pciaddr;
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ushort pcicmd;
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pci_map_t *pm;
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if (pci_dev_cnt >= MAX_PCI_DEVS) {
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puts("Too many PCI devices\n");
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return;
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}
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pm = &pci_map[pci_dev_cnt++];
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pm->pci_bus = bus;
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pm->pci_devfn = devfn;
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for (i=0; i<6; i++) {
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qs_pci_write_config_dword(bus, devfn, PCI_BASE_ADDRESS_0 + (i * 4), -1);
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qs_pci_read_config_dword(bus, devfn, PCI_BASE_ADDRESS_0 + (i * 4),
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&pciaddr);
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pm->pci_addrs[i] = pciaddr;
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qs_pci_read_config_word(bus, devfn, PCI_COMMAND, &pcicmd);
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pm->pci_command = pcicmd;
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}
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}
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/* Map the cards into the PCI space. The PCI has separate memory
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* and I/O spaces. In addition, some memory devices require mapping
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* below 1M. The least significant 4 bits of the address register
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* provide information. If this is an I/O device, only the LS bit
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* is used to indicate that, so I/O devices can be mapped to a two byte
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* boundard. Memory addresses can be mapped to a 32 byte boundary.
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* The QSpan implementations usually have a 1Gbyte space for each
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* memory and I/O spaces.
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*
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* This isn't a terribly fancy algorithm. I just map the spaces from
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* the top starting with the largest address space. When finished,
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* the registers are written and the card enabled.
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*
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* While the Tundra can map a large address space on most boards, we
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* need to be careful because it may overlap other devices (like IMMR).
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*/
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#define MEMORY_SPACE_SIZE 0x20000000
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#define IO_SPACE_SIZE 0x20000000
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void
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map_pci_addrs()
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{
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uint pci_mem_top, pci_mem_low;
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uint pci_io_top;
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uint addr_mask, reg_addr, space;
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int i, j;
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pci_map_t *pm;
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pci_mem_top = MEMORY_SPACE_SIZE;
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pci_io_top = IO_SPACE_SIZE;
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pci_mem_low = (1 * 1024 * 1024); /* Below one meg addresses */
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/* We can't map anything more than the maximum space, but test
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* for it anyway to catch devices out of range.
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*/
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addr_mask = 0x80000000;
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do {
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space = (~addr_mask) + 1; /* Size of the space */
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for (i=0; i<pci_dev_cnt; i++) {
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pm = &pci_map[i];
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for (j=0; j<6; j++) {
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/* If the MS bit is not set, this has either
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* already been mapped, or is not used.
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*/
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reg_addr = pm->pci_addrs[j];
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if ((reg_addr & 0x80000000) == 0)
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continue;
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if (reg_addr & PCI_BASE_ADDRESS_SPACE_IO) {
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if ((reg_addr & PCI_BASE_ADDRESS_IO_MASK) != addr_mask)
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continue;
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if (pci_io_top < space) {
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puts("Out of PCI I/O space\n");
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}
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else {
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pci_io_top -= space;
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pm->pci_addrs[j] = pci_io_top;
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pm->pci_command |= PCI_COMMAND_IO;
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}
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}
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else {
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if ((reg_addr & PCI_BASE_ADDRESS_MEM_MASK) != addr_mask)
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continue;
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/* Memory space. Test if below 1M.
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*/
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if (reg_addr & PCI_BASE_ADDRESS_MEM_TYPE_1M) {
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if (pci_mem_low < space) {
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puts("Out of PCI 1M space\n");
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}
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else {
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pci_mem_low -= space;
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pm->pci_addrs[j] = pci_mem_low;
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}
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}
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else {
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if (pci_mem_top < space) {
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puts("Out of PCI Mem space\n");
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}
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else {
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pci_mem_top -= space;
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pm->pci_addrs[j] = pci_mem_top;
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}
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}
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pm->pci_command |= PCI_COMMAND_MEMORY;
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}
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}
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}
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addr_mask >>= 1;
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addr_mask |= 0x80000000;
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} while (addr_mask != 0xfffffffe);
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/* Now, run the list one more time and map everything.
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*/
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for (i=0; i<pci_dev_cnt; i++) {
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pm = &pci_map[i];
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for (j=0; j<6; j++) {
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qs_pci_write_config_dword(pm->pci_bus, pm->pci_devfn,
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PCI_BASE_ADDRESS_0 + (j * 4), pm->pci_addrs[j]);
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}
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/* Enable memory or address mapping.
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*/
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qs_pci_write_config_word(pm->pci_bus, pm->pci_devfn, PCI_COMMAND,
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pm->pci_command);
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}
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}
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