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413 lines
10 KiB
413 lines
10 KiB
/*
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* Code to handle x86 style IRQs plus some generic interrupt stuff.
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*
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* Copyright (C) 1992 Linus Torvalds
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* Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle
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* Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
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* Copyright (C) 1999-2000 Grant Grundler
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* Copyright (c) 2005 Matthew Wilcox
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/bitops.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel_stat.h>
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#include <linux/seq_file.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <asm/io.h>
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#include <asm/smp.h>
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#undef PARISC_IRQ_CR16_COUNTS
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extern irqreturn_t timer_interrupt(int, void *, struct pt_regs *);
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extern irqreturn_t ipi_interrupt(int, void *, struct pt_regs *);
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#define EIEM_MASK(irq) (1UL<<(CPU_IRQ_MAX - irq))
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/* Bits in EIEM correlate with cpu_irq_action[].
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** Numbered *Big Endian*! (ie bit 0 is MSB)
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*/
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static volatile unsigned long cpu_eiem = 0;
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static void cpu_disable_irq(unsigned int irq)
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{
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unsigned long eirr_bit = EIEM_MASK(irq);
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cpu_eiem &= ~eirr_bit;
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/* Do nothing on the other CPUs. If they get this interrupt,
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* The & cpu_eiem in the do_cpu_irq_mask() ensures they won't
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* handle it, and the set_eiem() at the bottom will ensure it
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* then gets disabled */
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}
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static void cpu_enable_irq(unsigned int irq)
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{
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unsigned long eirr_bit = EIEM_MASK(irq);
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cpu_eiem |= eirr_bit;
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/* FIXME: while our interrupts aren't nested, we cannot reset
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* the eiem mask if we're already in an interrupt. Once we
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* implement nested interrupts, this can go away
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*/
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if (!in_interrupt())
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set_eiem(cpu_eiem);
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/* This is just a simple NOP IPI. But what it does is cause
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* all the other CPUs to do a set_eiem(cpu_eiem) at the end
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* of the interrupt handler */
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smp_send_all_nop();
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}
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static unsigned int cpu_startup_irq(unsigned int irq)
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{
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cpu_enable_irq(irq);
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return 0;
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}
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void no_ack_irq(unsigned int irq) { }
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void no_end_irq(unsigned int irq) { }
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#ifdef CONFIG_SMP
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int cpu_check_affinity(unsigned int irq, cpumask_t *dest)
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{
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int cpu_dest;
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/* timer and ipi have to always be received on all CPUs */
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if (irq == TIMER_IRQ || irq == IPI_IRQ) {
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/* Bad linux design decision. The mask has already
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* been set; we must reset it */
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irq_desc[irq].affinity = CPU_MASK_ALL;
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return -EINVAL;
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}
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/* whatever mask they set, we just allow one CPU */
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cpu_dest = first_cpu(*dest);
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*dest = cpumask_of_cpu(cpu_dest);
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return 0;
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}
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static void cpu_set_affinity_irq(unsigned int irq, cpumask_t dest)
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{
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if (cpu_check_affinity(irq, &dest))
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return;
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irq_desc[irq].affinity = dest;
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}
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#endif
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static struct hw_interrupt_type cpu_interrupt_type = {
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.typename = "CPU",
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.startup = cpu_startup_irq,
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.shutdown = cpu_disable_irq,
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.enable = cpu_enable_irq,
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.disable = cpu_disable_irq,
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.ack = no_ack_irq,
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.end = no_end_irq,
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#ifdef CONFIG_SMP
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.set_affinity = cpu_set_affinity_irq,
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#endif
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/* XXX: Needs to be written. We managed without it so far, but
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* we really ought to write it.
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*/
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.retrigger = NULL,
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};
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int show_interrupts(struct seq_file *p, void *v)
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{
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int i = *(loff_t *) v, j;
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unsigned long flags;
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if (i == 0) {
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seq_puts(p, " ");
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for_each_online_cpu(j)
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seq_printf(p, " CPU%d", j);
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#ifdef PARISC_IRQ_CR16_COUNTS
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seq_printf(p, " [min/avg/max] (CPU cycle counts)");
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#endif
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seq_putc(p, '\n');
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}
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if (i < NR_IRQS) {
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struct irqaction *action;
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spin_lock_irqsave(&irq_desc[i].lock, flags);
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action = irq_desc[i].action;
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if (!action)
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goto skip;
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seq_printf(p, "%3d: ", i);
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#ifdef CONFIG_SMP
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
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#else
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seq_printf(p, "%10u ", kstat_irqs(i));
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#endif
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seq_printf(p, " %14s", irq_desc[i].chip->typename);
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#ifndef PARISC_IRQ_CR16_COUNTS
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seq_printf(p, " %s", action->name);
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while ((action = action->next))
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seq_printf(p, ", %s", action->name);
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#else
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for ( ;action; action = action->next) {
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unsigned int k, avg, min, max;
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min = max = action->cr16_hist[0];
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for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) {
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int hist = action->cr16_hist[k];
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if (hist) {
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avg += hist;
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} else
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break;
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if (hist > max) max = hist;
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if (hist < min) min = hist;
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}
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avg /= k;
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seq_printf(p, " %s[%d/%d/%d]", action->name,
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min,avg,max);
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}
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#endif
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seq_putc(p, '\n');
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skip:
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spin_unlock_irqrestore(&irq_desc[i].lock, flags);
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}
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return 0;
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}
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/*
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** The following form a "set": Virtual IRQ, Transaction Address, Trans Data.
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** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit.
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**
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** To use txn_XXX() interfaces, get a Virtual IRQ first.
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** Then use that to get the Transaction address and data.
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*/
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int cpu_claim_irq(unsigned int irq, struct hw_interrupt_type *type, void *data)
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{
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if (irq_desc[irq].action)
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return -EBUSY;
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if (irq_desc[irq].chip != &cpu_interrupt_type)
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return -EBUSY;
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if (type) {
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irq_desc[irq].chip = type;
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irq_desc[irq].chip_data = data;
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cpu_interrupt_type.enable(irq);
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}
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return 0;
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}
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int txn_claim_irq(int irq)
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{
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return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq;
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}
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/*
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* The bits_wide parameter accommodates the limitations of the HW/SW which
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* use these bits:
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* Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register)
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* V-class (EPIC): 6 bits
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* N/L/A-class (iosapic): 8 bits
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* PCI 2.2 MSI: 16 bits
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* Some PCI devices: 32 bits (Symbios SCSI/ATM/HyperFabric)
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*
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* On the service provider side:
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* o PA 1.1 (and PA2.0 narrow mode) 5-bits (width of EIR register)
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* o PA 2.0 wide mode 6-bits (per processor)
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* o IA64 8-bits (0-256 total)
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*
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* So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported
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* by the processor...and the N/L-class I/O subsystem supports more bits than
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* PA2.0 has. The first case is the problem.
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*/
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int txn_alloc_irq(unsigned int bits_wide)
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{
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int irq;
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/* never return irq 0 cause that's the interval timer */
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for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) {
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if (cpu_claim_irq(irq, NULL, NULL) < 0)
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continue;
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if ((irq - CPU_IRQ_BASE) >= (1 << bits_wide))
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continue;
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return irq;
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}
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/* unlikely, but be prepared */
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return -1;
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}
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unsigned long txn_affinity_addr(unsigned int irq, int cpu)
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{
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#ifdef CONFIG_SMP
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irq_desc[irq].affinity = cpumask_of_cpu(cpu);
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#endif
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return cpu_data[cpu].txn_addr;
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}
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unsigned long txn_alloc_addr(unsigned int virt_irq)
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{
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static int next_cpu = -1;
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next_cpu++; /* assign to "next" CPU we want this bugger on */
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/* validate entry */
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while ((next_cpu < NR_CPUS) && (!cpu_data[next_cpu].txn_addr ||
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!cpu_online(next_cpu)))
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next_cpu++;
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if (next_cpu >= NR_CPUS)
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next_cpu = 0; /* nothing else, assign monarch */
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return txn_affinity_addr(virt_irq, next_cpu);
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}
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unsigned int txn_alloc_data(unsigned int virt_irq)
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{
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return virt_irq - CPU_IRQ_BASE;
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}
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/* ONLY called from entry.S:intr_extint() */
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void do_cpu_irq_mask(struct pt_regs *regs)
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{
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unsigned long eirr_val;
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irq_enter();
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/*
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* Don't allow TIMER or IPI nested interrupts.
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* Allowing any single interrupt to nest can lead to that CPU
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* handling interrupts with all enabled interrupts unmasked.
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*/
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set_eiem(0UL);
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/* 1) only process IRQs that are enabled/unmasked (cpu_eiem)
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* 2) We loop here on EIRR contents in order to avoid
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* nested interrupts or having to take another interrupt
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* when we could have just handled it right away.
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*/
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for (;;) {
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unsigned long bit = (1UL << (BITS_PER_LONG - 1));
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unsigned int irq;
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eirr_val = mfctl(23) & cpu_eiem;
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if (!eirr_val)
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break;
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mtctl(eirr_val, 23); /* reset bits we are going to process */
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/* Work our way from MSb to LSb...same order we alloc EIRs */
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for (irq = TIMER_IRQ; eirr_val && bit; bit>>=1, irq++) {
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#ifdef CONFIG_SMP
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cpumask_t dest = irq_desc[irq].affinity;
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#endif
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if (!(bit & eirr_val))
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continue;
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/* clear bit in mask - can exit loop sooner */
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eirr_val &= ~bit;
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#ifdef CONFIG_SMP
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/* FIXME: because generic set affinity mucks
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* with the affinity before sending it to us
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* we can get the situation where the affinity is
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* wrong for our CPU type interrupts */
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if (irq != TIMER_IRQ && irq != IPI_IRQ &&
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!cpu_isset(smp_processor_id(), dest)) {
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int cpu = first_cpu(dest);
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printk(KERN_DEBUG "redirecting irq %d from CPU %d to %d\n",
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irq, smp_processor_id(), cpu);
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gsc_writel(irq + CPU_IRQ_BASE,
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cpu_data[cpu].hpa);
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continue;
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}
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#endif
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__do_IRQ(irq, regs);
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}
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}
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set_eiem(cpu_eiem); /* restore original mask */
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irq_exit();
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}
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static struct irqaction timer_action = {
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.handler = timer_interrupt,
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.name = "timer",
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.flags = IRQF_DISABLED,
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};
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#ifdef CONFIG_SMP
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static struct irqaction ipi_action = {
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.handler = ipi_interrupt,
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.name = "IPI",
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.flags = IRQF_DISABLED,
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};
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#endif
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static void claim_cpu_irqs(void)
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{
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int i;
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for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
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irq_desc[i].chip = &cpu_interrupt_type;
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}
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irq_desc[TIMER_IRQ].action = &timer_action;
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irq_desc[TIMER_IRQ].status |= IRQ_PER_CPU;
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#ifdef CONFIG_SMP
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irq_desc[IPI_IRQ].action = &ipi_action;
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irq_desc[IPI_IRQ].status = IRQ_PER_CPU;
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#endif
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}
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void __init init_IRQ(void)
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{
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local_irq_disable(); /* PARANOID - should already be disabled */
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mtctl(~0UL, 23); /* EIRR : clear all pending external intr */
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claim_cpu_irqs();
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#ifdef CONFIG_SMP
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if (!cpu_eiem)
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cpu_eiem = EIEM_MASK(IPI_IRQ) | EIEM_MASK(TIMER_IRQ);
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#else
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cpu_eiem = EIEM_MASK(TIMER_IRQ);
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#endif
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set_eiem(cpu_eiem); /* EIEM : enable all external intr */
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}
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void ack_bad_irq(unsigned int irq)
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{
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printk("unexpected IRQ %d\n", irq);
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}
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