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14 lines
414 B
14 lines
414 B
#ifndef _CRIS_ARCH_TLB_H
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#define _CRIS_ARCH_TLB_H
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/*
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* The TLB is a 64-entry cache. Each entry has a 8-bit page_id that is used
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* to store the "process" it belongs to (=> fast mm context switch). The
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* last page_id is never used so we can make TLB entries that never matches.
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*/
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#define NUM_TLB_ENTRIES 64
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#define NUM_PAGEID 256
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#define INVALID_PAGEID 255
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#define NO_CONTEXT -1
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#endif /* _CRIS_ARCH_TLB_H */
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