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42 lines
1.1 KiB
42 lines
1.1 KiB
/*
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* The ARM LDRD and Thumb LDRSB instructions use bit 20/11 (ARM/Thumb)
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* differently than every other instruction, so it is set to 0 (write)
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* even though the instructions are read instructions. This means that
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* during an abort the instructions will be treated as a write and the
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* handler will raise a signal from unwriteable locations if they
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* fault. We have to specifically check for these instructions
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* from the abort handlers to treat them properly.
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*
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*/
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.macro do_thumb_abort
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tst r3, #PSR_T_BIT
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beq not_thumb
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ldrh r3, [r2] @ Read aborted Thumb instruction
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and r3, r3, # 0xfe00 @ Mask opcode field
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cmp r3, # 0x5600 @ Is it ldrsb?
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orreq r3, r3, #1 << 11 @ Set L-bit if yes
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tst r3, #1 << 11 @ L = 0 -> write
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orreq r1, r1, #1 << 11 @ yes.
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mov pc, lr
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not_thumb:
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.endm
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/*
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* We check for the following insturction encoding for LDRD.
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*
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* [27:25] == 0
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* [7:4] == 1101
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* [20] == 0
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*/
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.macro do_ldrd_abort
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tst r3, #0x0e000000 @ [27:25] == 0
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bne not_ldrd
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and r2, r3, #0x000000f0 @ [7:4] == 1101
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cmp r2, #0x000000d0
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bne not_ldrd
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tst r3, #1 << 20 @ [20] == 0
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moveq pc, lr
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not_ldrd:
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.endm
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