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817 lines
20 KiB
817 lines
20 KiB
/* linux/drivers/mtd/nand/s3c2410.c
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*
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* Copyright (c) 2004,2005 Simtec Electronics
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* http://www.simtec.co.uk/products/SWLINUX/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* Samsung S3C2410/S3C240 NAND driver
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*
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* Changelog:
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* 21-Sep-2004 BJD Initial version
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* 23-Sep-2004 BJD Mulitple device support
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* 28-Sep-2004 BJD Fixed ECC placement for Hardware mode
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* 12-Oct-2004 BJD Fixed errors in use of platform data
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* 18-Feb-2005 BJD Fix sparse errors
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* 14-Mar-2005 BJD Applied tglx's code reduction patch
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* 02-May-2005 BJD Fixed s3c2440 support
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* 02-May-2005 BJD Reduced hwcontrol decode
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* 20-Jun-2005 BJD Updated s3c2440 support, fixed timing bug
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* 08-Jul-2005 BJD Fix OOPS when no platform data supplied
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* 20-Oct-2005 BJD Fix timing calculation bug
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* 14-Jan-2006 BJD Allow clock to be stopped when idle
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*
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* $Id: s3c2410.c,v 1.23 2006/04/01 18:06:29 bjd Exp $
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
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#define DEBUG
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#endif
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/ioport.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/mtd/partitions.h>
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#include <asm/io.h>
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#include <asm/arch/regs-nand.h>
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#include <asm/arch/nand.h>
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#ifdef CONFIG_MTD_NAND_S3C2410_HWECC
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static int hardware_ecc = 1;
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#else
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static int hardware_ecc = 0;
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#endif
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#ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP
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static int clock_stop = 1;
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#else
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static const int clock_stop = 0;
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#endif
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/* new oob placement block for use with hardware ecc generation
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*/
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static struct nand_ecclayout nand_hw_eccoob = {
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.eccbytes = 3,
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.eccpos = {0, 1, 2},
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.oobfree = {{8, 8}}
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};
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/* controller and mtd information */
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struct s3c2410_nand_info;
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struct s3c2410_nand_mtd {
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struct mtd_info mtd;
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struct nand_chip chip;
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struct s3c2410_nand_set *set;
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struct s3c2410_nand_info *info;
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int scan_res;
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};
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enum s3c_cpu_type {
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TYPE_S3C2410,
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TYPE_S3C2412,
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TYPE_S3C2440,
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};
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/* overview of the s3c2410 nand state */
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struct s3c2410_nand_info {
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/* mtd info */
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struct nand_hw_control controller;
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struct s3c2410_nand_mtd *mtds;
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struct s3c2410_platform_nand *platform;
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/* device info */
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struct device *device;
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struct resource *area;
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struct clk *clk;
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void __iomem *regs;
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void __iomem *sel_reg;
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int sel_bit;
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int mtd_count;
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enum s3c_cpu_type cpu_type;
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};
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/* conversion functions */
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static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
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{
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return container_of(mtd, struct s3c2410_nand_mtd, mtd);
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}
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static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
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{
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return s3c2410_nand_mtd_toours(mtd)->info;
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}
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static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev)
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{
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return platform_get_drvdata(dev);
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}
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static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev)
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{
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return dev->dev.platform_data;
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}
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static inline int allow_clk_stop(struct s3c2410_nand_info *info)
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{
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return clock_stop;
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}
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/* timing calculations */
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#define NS_IN_KHZ 1000000
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static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max)
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{
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int result;
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result = (wanted * clk) / NS_IN_KHZ;
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result++;
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pr_debug("result %d from %ld, %d\n", result, clk, wanted);
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if (result > max) {
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printk("%d ns is too big for current clock rate %ld\n", wanted, clk);
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return -1;
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}
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if (result < 1)
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result = 1;
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return result;
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}
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#define to_ns(ticks,clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
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/* controller setup */
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static int s3c2410_nand_inithw(struct s3c2410_nand_info *info,
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struct platform_device *pdev)
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{
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struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
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unsigned long clkrate = clk_get_rate(info->clk);
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int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4;
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int tacls, twrph0, twrph1;
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unsigned long cfg = 0;
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/* calculate the timing information for the controller */
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clkrate /= 1000; /* turn clock into kHz for ease of use */
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if (plat != NULL) {
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tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max);
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twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8);
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twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8);
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} else {
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/* default timings */
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tacls = tacls_max;
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twrph0 = 8;
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twrph1 = 8;
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}
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if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
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dev_err(info->device, "cannot get suitable timings\n");
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return -EINVAL;
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}
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dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
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tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), twrph1, to_ns(twrph1, clkrate));
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switch (info->cpu_type) {
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case TYPE_S3C2410:
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cfg = S3C2410_NFCONF_EN;
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cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
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cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
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cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
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break;
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case TYPE_S3C2440:
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case TYPE_S3C2412:
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cfg = S3C2440_NFCONF_TACLS(tacls - 1);
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cfg |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
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cfg |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
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/* enable the controller and de-assert nFCE */
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writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT);
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}
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dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
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writel(cfg, info->regs + S3C2410_NFCONF);
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return 0;
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}
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/* select chip */
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static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
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{
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struct s3c2410_nand_info *info;
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struct s3c2410_nand_mtd *nmtd;
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struct nand_chip *this = mtd->priv;
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unsigned long cur;
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nmtd = this->priv;
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info = nmtd->info;
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if (chip != -1 && allow_clk_stop(info))
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clk_enable(info->clk);
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cur = readl(info->sel_reg);
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if (chip == -1) {
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cur |= info->sel_bit;
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} else {
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if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
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dev_err(info->device, "invalid chip %d\n", chip);
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return;
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}
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if (info->platform != NULL) {
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if (info->platform->select_chip != NULL)
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(info->platform->select_chip) (nmtd->set, chip);
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}
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cur &= ~info->sel_bit;
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}
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writel(cur, info->sel_reg);
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if (chip == -1 && allow_clk_stop(info))
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clk_disable(info->clk);
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}
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/* s3c2410_nand_hwcontrol
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*
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* Issue command and address cycles to the chip
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*/
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static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
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if (cmd == NAND_CMD_NONE)
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return;
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if (ctrl & NAND_CLE)
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writeb(cmd, info->regs + S3C2410_NFCMD);
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else
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writeb(cmd, info->regs + S3C2410_NFADDR);
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}
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/* command and control functions */
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static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
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if (cmd == NAND_CMD_NONE)
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return;
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if (ctrl & NAND_CLE)
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writeb(cmd, info->regs + S3C2440_NFCMD);
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else
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writeb(cmd, info->regs + S3C2440_NFADDR);
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}
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/* s3c2410_nand_devready()
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*
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* returns 0 if the nand is busy, 1 if it is ready
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*/
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static int s3c2410_nand_devready(struct mtd_info *mtd)
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{
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struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
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return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
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}
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static int s3c2440_nand_devready(struct mtd_info *mtd)
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{
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struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
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return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
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}
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static int s3c2412_nand_devready(struct mtd_info *mtd)
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{
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struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
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return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY;
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}
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/* ECC handling functions */
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static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
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u_char *read_ecc, u_char *calc_ecc)
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{
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pr_debug("s3c2410_nand_correct_data(%p,%p,%p,%p)\n", mtd, dat, read_ecc, calc_ecc);
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pr_debug("eccs: read %02x,%02x,%02x vs calc %02x,%02x,%02x\n",
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read_ecc[0], read_ecc[1], read_ecc[2], calc_ecc[0], calc_ecc[1], calc_ecc[2]);
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if (read_ecc[0] == calc_ecc[0] && read_ecc[1] == calc_ecc[1] && read_ecc[2] == calc_ecc[2])
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return 0;
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/* we curently have no method for correcting the error */
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return -1;
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}
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/* ECC functions
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*
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* These allow the s3c2410 and s3c2440 to use the controller's ECC
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* generator block to ECC the data as it passes through]
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*/
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static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
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unsigned long ctrl;
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ctrl = readl(info->regs + S3C2410_NFCONF);
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ctrl |= S3C2410_NFCONF_INITECC;
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writel(ctrl, info->regs + S3C2410_NFCONF);
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}
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static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
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unsigned long ctrl;
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ctrl = readl(info->regs + S3C2440_NFCONT);
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writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);
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}
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static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
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{
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struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
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ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
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ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
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ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
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pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]);
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return 0;
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}
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static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
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{
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struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
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unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);
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ecc_code[0] = ecc;
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ecc_code[1] = ecc >> 8;
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ecc_code[2] = ecc >> 16;
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pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]);
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return 0;
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}
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/* over-ride the standard functions for a little more speed. We can
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* use read/write block to move the data buffers to/from the controller
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*/
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static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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{
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struct nand_chip *this = mtd->priv;
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readsb(this->IO_ADDR_R, buf, len);
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}
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static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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struct nand_chip *this = mtd->priv;
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writesb(this->IO_ADDR_W, buf, len);
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}
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/* device management functions */
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static int s3c2410_nand_remove(struct platform_device *pdev)
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{
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struct s3c2410_nand_info *info = to_nand_info(pdev);
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platform_set_drvdata(pdev, NULL);
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if (info == NULL)
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return 0;
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/* first thing we need to do is release all our mtds
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* and their partitions, then go through freeing the
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* resources used
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*/
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if (info->mtds != NULL) {
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struct s3c2410_nand_mtd *ptr = info->mtds;
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int mtdno;
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for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
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pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
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nand_release(&ptr->mtd);
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}
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kfree(info->mtds);
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}
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/* free the common resources */
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if (info->clk != NULL && !IS_ERR(info->clk)) {
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if (!allow_clk_stop(info))
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clk_disable(info->clk);
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clk_put(info->clk);
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}
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if (info->regs != NULL) {
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iounmap(info->regs);
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info->regs = NULL;
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}
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if (info->area != NULL) {
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release_resource(info->area);
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kfree(info->area);
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info->area = NULL;
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}
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kfree(info);
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return 0;
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}
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#ifdef CONFIG_MTD_PARTITIONS
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static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
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struct s3c2410_nand_mtd *mtd,
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struct s3c2410_nand_set *set)
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{
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if (set == NULL)
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return add_mtd_device(&mtd->mtd);
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if (set->nr_partitions > 0 && set->partitions != NULL) {
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return add_mtd_partitions(&mtd->mtd, set->partitions, set->nr_partitions);
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}
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return add_mtd_device(&mtd->mtd);
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|
}
|
|
#else
|
|
static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
|
|
struct s3c2410_nand_mtd *mtd,
|
|
struct s3c2410_nand_set *set)
|
|
{
|
|
return add_mtd_device(&mtd->mtd);
|
|
}
|
|
#endif
|
|
|
|
/* s3c2410_nand_init_chip
|
|
*
|
|
* init a single instance of an chip
|
|
*/
|
|
|
|
static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
|
|
struct s3c2410_nand_mtd *nmtd,
|
|
struct s3c2410_nand_set *set)
|
|
{
|
|
struct nand_chip *chip = &nmtd->chip;
|
|
void __iomem *regs = info->regs;
|
|
|
|
chip->write_buf = s3c2410_nand_write_buf;
|
|
chip->read_buf = s3c2410_nand_read_buf;
|
|
chip->select_chip = s3c2410_nand_select_chip;
|
|
chip->chip_delay = 50;
|
|
chip->priv = nmtd;
|
|
chip->options = 0;
|
|
chip->controller = &info->controller;
|
|
|
|
switch (info->cpu_type) {
|
|
case TYPE_S3C2410:
|
|
chip->IO_ADDR_W = regs + S3C2410_NFDATA;
|
|
info->sel_reg = regs + S3C2410_NFCONF;
|
|
info->sel_bit = S3C2410_NFCONF_nFCE;
|
|
chip->cmd_ctrl = s3c2410_nand_hwcontrol;
|
|
chip->dev_ready = s3c2410_nand_devready;
|
|
break;
|
|
|
|
case TYPE_S3C2440:
|
|
chip->IO_ADDR_W = regs + S3C2440_NFDATA;
|
|
info->sel_reg = regs + S3C2440_NFCONT;
|
|
info->sel_bit = S3C2440_NFCONT_nFCE;
|
|
chip->cmd_ctrl = s3c2440_nand_hwcontrol;
|
|
chip->dev_ready = s3c2440_nand_devready;
|
|
break;
|
|
|
|
case TYPE_S3C2412:
|
|
chip->IO_ADDR_W = regs + S3C2440_NFDATA;
|
|
info->sel_reg = regs + S3C2440_NFCONT;
|
|
info->sel_bit = S3C2412_NFCONT_nFCE0;
|
|
chip->cmd_ctrl = s3c2440_nand_hwcontrol;
|
|
chip->dev_ready = s3c2412_nand_devready;
|
|
|
|
if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT)
|
|
dev_info(info->device, "System booted from NAND\n");
|
|
|
|
break;
|
|
}
|
|
|
|
chip->IO_ADDR_R = chip->IO_ADDR_W;
|
|
|
|
nmtd->info = info;
|
|
nmtd->mtd.priv = chip;
|
|
nmtd->mtd.owner = THIS_MODULE;
|
|
nmtd->set = set;
|
|
|
|
if (hardware_ecc) {
|
|
chip->ecc.calculate = s3c2410_nand_calculate_ecc;
|
|
chip->ecc.correct = s3c2410_nand_correct_data;
|
|
chip->ecc.mode = NAND_ECC_HW;
|
|
chip->ecc.size = 512;
|
|
chip->ecc.bytes = 3;
|
|
chip->ecc.layout = &nand_hw_eccoob;
|
|
|
|
switch (info->cpu_type) {
|
|
case TYPE_S3C2410:
|
|
chip->ecc.hwctl = s3c2410_nand_enable_hwecc;
|
|
chip->ecc.calculate = s3c2410_nand_calculate_ecc;
|
|
break;
|
|
|
|
case TYPE_S3C2412:
|
|
case TYPE_S3C2440:
|
|
chip->ecc.hwctl = s3c2440_nand_enable_hwecc;
|
|
chip->ecc.calculate = s3c2440_nand_calculate_ecc;
|
|
break;
|
|
|
|
}
|
|
} else {
|
|
chip->ecc.mode = NAND_ECC_SOFT;
|
|
}
|
|
}
|
|
|
|
/* s3c2410_nand_probe
|
|
*
|
|
* called by device layer when it finds a device matching
|
|
* one our driver can handled. This code checks to see if
|
|
* it can allocate all necessary resources then calls the
|
|
* nand layer to look for devices
|
|
*/
|
|
|
|
static int s3c24xx_nand_probe(struct platform_device *pdev,
|
|
enum s3c_cpu_type cpu_type)
|
|
{
|
|
struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
|
|
struct s3c2410_nand_info *info;
|
|
struct s3c2410_nand_mtd *nmtd;
|
|
struct s3c2410_nand_set *sets;
|
|
struct resource *res;
|
|
int err = 0;
|
|
int size;
|
|
int nr_sets;
|
|
int setno;
|
|
|
|
pr_debug("s3c2410_nand_probe(%p)\n", pdev);
|
|
|
|
info = kmalloc(sizeof(*info), GFP_KERNEL);
|
|
if (info == NULL) {
|
|
dev_err(&pdev->dev, "no memory for flash info\n");
|
|
err = -ENOMEM;
|
|
goto exit_error;
|
|
}
|
|
|
|
memzero(info, sizeof(*info));
|
|
platform_set_drvdata(pdev, info);
|
|
|
|
spin_lock_init(&info->controller.lock);
|
|
init_waitqueue_head(&info->controller.wq);
|
|
|
|
/* get the clock source and enable it */
|
|
|
|
info->clk = clk_get(&pdev->dev, "nand");
|
|
if (IS_ERR(info->clk)) {
|
|
dev_err(&pdev->dev, "failed to get clock");
|
|
err = -ENOENT;
|
|
goto exit_error;
|
|
}
|
|
|
|
clk_enable(info->clk);
|
|
|
|
/* allocate and map the resource */
|
|
|
|
/* currently we assume we have the one resource */
|
|
res = pdev->resource;
|
|
size = res->end - res->start + 1;
|
|
|
|
info->area = request_mem_region(res->start, size, pdev->name);
|
|
|
|
if (info->area == NULL) {
|
|
dev_err(&pdev->dev, "cannot reserve register region\n");
|
|
err = -ENOENT;
|
|
goto exit_error;
|
|
}
|
|
|
|
info->device = &pdev->dev;
|
|
info->platform = plat;
|
|
info->regs = ioremap(res->start, size);
|
|
info->cpu_type = cpu_type;
|
|
|
|
if (info->regs == NULL) {
|
|
dev_err(&pdev->dev, "cannot reserve register region\n");
|
|
err = -EIO;
|
|
goto exit_error;
|
|
}
|
|
|
|
dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
|
|
|
|
/* initialise the hardware */
|
|
|
|
err = s3c2410_nand_inithw(info, pdev);
|
|
if (err != 0)
|
|
goto exit_error;
|
|
|
|
sets = (plat != NULL) ? plat->sets : NULL;
|
|
nr_sets = (plat != NULL) ? plat->nr_sets : 1;
|
|
|
|
info->mtd_count = nr_sets;
|
|
|
|
/* allocate our information */
|
|
|
|
size = nr_sets * sizeof(*info->mtds);
|
|
info->mtds = kmalloc(size, GFP_KERNEL);
|
|
if (info->mtds == NULL) {
|
|
dev_err(&pdev->dev, "failed to allocate mtd storage\n");
|
|
err = -ENOMEM;
|
|
goto exit_error;
|
|
}
|
|
|
|
memzero(info->mtds, size);
|
|
|
|
/* initialise all possible chips */
|
|
|
|
nmtd = info->mtds;
|
|
|
|
for (setno = 0; setno < nr_sets; setno++, nmtd++) {
|
|
pr_debug("initialising set %d (%p, info %p)\n", setno, nmtd, info);
|
|
|
|
s3c2410_nand_init_chip(info, nmtd, sets);
|
|
|
|
nmtd->scan_res = nand_scan(&nmtd->mtd, (sets) ? sets->nr_chips : 1);
|
|
|
|
if (nmtd->scan_res == 0) {
|
|
s3c2410_nand_add_partition(info, nmtd, sets);
|
|
}
|
|
|
|
if (sets != NULL)
|
|
sets++;
|
|
}
|
|
|
|
if (allow_clk_stop(info)) {
|
|
dev_info(&pdev->dev, "clock idle support enabled\n");
|
|
clk_disable(info->clk);
|
|
}
|
|
|
|
pr_debug("initialised ok\n");
|
|
return 0;
|
|
|
|
exit_error:
|
|
s3c2410_nand_remove(pdev);
|
|
|
|
if (err == 0)
|
|
err = -EINVAL;
|
|
return err;
|
|
}
|
|
|
|
/* PM Support */
|
|
#ifdef CONFIG_PM
|
|
|
|
static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
|
|
{
|
|
struct s3c2410_nand_info *info = platform_get_drvdata(dev);
|
|
|
|
if (info) {
|
|
if (!allow_clk_stop(info))
|
|
clk_disable(info->clk);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int s3c24xx_nand_resume(struct platform_device *dev)
|
|
{
|
|
struct s3c2410_nand_info *info = platform_get_drvdata(dev);
|
|
|
|
if (info) {
|
|
clk_enable(info->clk);
|
|
s3c2410_nand_inithw(info, dev);
|
|
|
|
if (allow_clk_stop(info))
|
|
clk_disable(info->clk);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#else
|
|
#define s3c24xx_nand_suspend NULL
|
|
#define s3c24xx_nand_resume NULL
|
|
#endif
|
|
|
|
/* driver device registration */
|
|
|
|
static int s3c2410_nand_probe(struct platform_device *dev)
|
|
{
|
|
return s3c24xx_nand_probe(dev, TYPE_S3C2410);
|
|
}
|
|
|
|
static int s3c2440_nand_probe(struct platform_device *dev)
|
|
{
|
|
return s3c24xx_nand_probe(dev, TYPE_S3C2440);
|
|
}
|
|
|
|
static int s3c2412_nand_probe(struct platform_device *dev)
|
|
{
|
|
return s3c24xx_nand_probe(dev, TYPE_S3C2412);
|
|
}
|
|
|
|
static struct platform_driver s3c2410_nand_driver = {
|
|
.probe = s3c2410_nand_probe,
|
|
.remove = s3c2410_nand_remove,
|
|
.suspend = s3c24xx_nand_suspend,
|
|
.resume = s3c24xx_nand_resume,
|
|
.driver = {
|
|
.name = "s3c2410-nand",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
static struct platform_driver s3c2440_nand_driver = {
|
|
.probe = s3c2440_nand_probe,
|
|
.remove = s3c2410_nand_remove,
|
|
.suspend = s3c24xx_nand_suspend,
|
|
.resume = s3c24xx_nand_resume,
|
|
.driver = {
|
|
.name = "s3c2440-nand",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
static struct platform_driver s3c2412_nand_driver = {
|
|
.probe = s3c2412_nand_probe,
|
|
.remove = s3c2410_nand_remove,
|
|
.suspend = s3c24xx_nand_suspend,
|
|
.resume = s3c24xx_nand_resume,
|
|
.driver = {
|
|
.name = "s3c2412-nand",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
static int __init s3c2410_nand_init(void)
|
|
{
|
|
printk("S3C24XX NAND Driver, (c) 2004 Simtec Electronics\n");
|
|
|
|
platform_driver_register(&s3c2412_nand_driver);
|
|
platform_driver_register(&s3c2440_nand_driver);
|
|
return platform_driver_register(&s3c2410_nand_driver);
|
|
}
|
|
|
|
static void __exit s3c2410_nand_exit(void)
|
|
{
|
|
platform_driver_unregister(&s3c2412_nand_driver);
|
|
platform_driver_unregister(&s3c2440_nand_driver);
|
|
platform_driver_unregister(&s3c2410_nand_driver);
|
|
}
|
|
|
|
module_init(s3c2410_nand_init);
|
|
module_exit(s3c2410_nand_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
|
|
MODULE_DESCRIPTION("S3C24XX MTD NAND driver");
|
|
|