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294 lines
8.0 KiB
294 lines
8.0 KiB
/*
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* PPC440GX system library
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*
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* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
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* Copyright (c) 2003 - 2006 Zultys Technologies
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <asm/ibm44x.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <syslib/ibm440gx_common.h>
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/*
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* Calculate 440GX clocks
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*/
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static inline u32 __fix_zero(u32 v, u32 def){
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return v ? v : def;
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}
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void __init ibm440gx_get_clocks(struct ibm44x_clocks* p, unsigned int sys_clk,
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unsigned int ser_clk)
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{
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u32 pllc = CPR_READ(DCRN_CPR_PLLC);
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u32 plld = CPR_READ(DCRN_CPR_PLLD);
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u32 uart0 = SDR_READ(DCRN_SDR_UART0);
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u32 uart1 = SDR_READ(DCRN_SDR_UART1);
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#ifdef CONFIG_440EP
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u32 uart2 = SDR_READ(DCRN_SDR_UART2);
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u32 uart3 = SDR_READ(DCRN_SDR_UART3);
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#endif
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/* Dividers */
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u32 fbdv = __fix_zero((plld >> 24) & 0x1f, 32);
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u32 fwdva = __fix_zero((plld >> 16) & 0xf, 16);
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u32 fwdvb = __fix_zero((plld >> 8) & 7, 8);
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u32 lfbdv = __fix_zero(plld & 0x3f, 64);
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u32 pradv0 = __fix_zero((CPR_READ(DCRN_CPR_PRIMAD) >> 24) & 7, 8);
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u32 prbdv0 = __fix_zero((CPR_READ(DCRN_CPR_PRIMBD) >> 24) & 7, 8);
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u32 opbdv0 = __fix_zero((CPR_READ(DCRN_CPR_OPBD) >> 24) & 3, 4);
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u32 perdv0 = __fix_zero((CPR_READ(DCRN_CPR_PERD) >> 24) & 3, 4);
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/* Input clocks for primary dividers */
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u32 clk_a, clk_b;
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if (pllc & 0x40000000){
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u32 m;
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/* Feedback path */
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switch ((pllc >> 24) & 7){
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case 0:
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/* PLLOUTx */
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m = ((pllc & 0x20000000) ? fwdvb : fwdva) * lfbdv;
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break;
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case 1:
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/* CPU */
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m = fwdva * pradv0;
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break;
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case 5:
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/* PERClk */
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m = fwdvb * prbdv0 * opbdv0 * perdv0;
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break;
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default:
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printk(KERN_EMERG "invalid PLL feedback source\n");
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goto bypass;
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}
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m *= fbdv;
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p->vco = sys_clk * m;
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clk_a = p->vco / fwdva;
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clk_b = p->vco / fwdvb;
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}
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else {
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bypass:
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/* Bypass system PLL */
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p->vco = 0;
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clk_a = clk_b = sys_clk;
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}
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p->cpu = clk_a / pradv0;
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p->plb = clk_b / prbdv0;
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p->opb = p->plb / opbdv0;
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p->ebc = p->opb / perdv0;
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/* UARTs clock */
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if (uart0 & 0x00800000)
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p->uart0 = ser_clk;
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else
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p->uart0 = p->plb / __fix_zero(uart0 & 0xff, 256);
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if (uart1 & 0x00800000)
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p->uart1 = ser_clk;
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else
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p->uart1 = p->plb / __fix_zero(uart1 & 0xff, 256);
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#ifdef CONFIG_440EP
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if (uart2 & 0x00800000)
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p->uart2 = ser_clk;
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else
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p->uart2 = p->plb / __fix_zero(uart2 & 0xff, 256);
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if (uart3 & 0x00800000)
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p->uart3 = ser_clk;
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else
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p->uart3 = p->plb / __fix_zero(uart3 & 0xff, 256);
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#endif
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}
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/* Issue L2C diagnostic command */
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static inline u32 l2c_diag(u32 addr)
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{
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mtdcr(DCRN_L2C0_ADDR, addr);
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mtdcr(DCRN_L2C0_CMD, L2C_CMD_DIAG);
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while (!(mfdcr(DCRN_L2C0_SR) & L2C_SR_CC)) ;
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return mfdcr(DCRN_L2C0_DATA);
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}
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static irqreturn_t l2c_error_handler(int irq, void* dev, struct pt_regs* regs)
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{
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u32 sr = mfdcr(DCRN_L2C0_SR);
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if (sr & L2C_SR_CPE){
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/* Read cache trapped address */
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u32 addr = l2c_diag(0x42000000);
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printk(KERN_EMERG "L2C: Cache Parity Error, addr[16:26] = 0x%08x\n", addr);
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}
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if (sr & L2C_SR_TPE){
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/* Read tag trapped address */
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u32 addr = l2c_diag(0x82000000) >> 16;
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printk(KERN_EMERG "L2C: Tag Parity Error, addr[16:26] = 0x%08x\n", addr);
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}
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/* Clear parity errors */
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if (sr & (L2C_SR_CPE | L2C_SR_TPE)){
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mtdcr(DCRN_L2C0_ADDR, 0);
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mtdcr(DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
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} else
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printk(KERN_EMERG "L2C: LRU error\n");
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return IRQ_HANDLED;
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}
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/* Enable L2 cache */
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void __init ibm440gx_l2c_enable(void){
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u32 r;
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unsigned long flags;
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/* Install error handler */
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if (request_irq(87, l2c_error_handler, IRQF_DISABLED, "L2C", 0) < 0){
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printk(KERN_ERR "Cannot install L2C error handler, cache is not enabled\n");
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return;
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}
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local_irq_save(flags);
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asm volatile ("sync" ::: "memory");
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/* Disable SRAM */
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mtdcr(DCRN_SRAM0_DPC, mfdcr(DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE);
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mtdcr(DCRN_SRAM0_SB0CR, mfdcr(DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK);
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mtdcr(DCRN_SRAM0_SB1CR, mfdcr(DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK);
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mtdcr(DCRN_SRAM0_SB2CR, mfdcr(DCRN_SRAM0_SB2CR) & ~SRAM_SBCR_BU_MASK);
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mtdcr(DCRN_SRAM0_SB3CR, mfdcr(DCRN_SRAM0_SB3CR) & ~SRAM_SBCR_BU_MASK);
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/* Enable L2_MODE without ICU/DCU */
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r = mfdcr(DCRN_L2C0_CFG) & ~(L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_SS_MASK);
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r |= L2C_CFG_L2M | L2C_CFG_SS_256;
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mtdcr(DCRN_L2C0_CFG, r);
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mtdcr(DCRN_L2C0_ADDR, 0);
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/* Hardware Clear Command */
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mtdcr(DCRN_L2C0_CMD, L2C_CMD_HCC);
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while (!(mfdcr(DCRN_L2C0_SR) & L2C_SR_CC)) ;
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/* Clear Cache Parity and Tag Errors */
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mtdcr(DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
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/* Enable 64G snoop region starting at 0 */
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r = mfdcr(DCRN_L2C0_SNP0) & ~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK);
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r |= L2C_SNP_SSR_32G | L2C_SNP_ESR;
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mtdcr(DCRN_L2C0_SNP0, r);
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r = mfdcr(DCRN_L2C0_SNP1) & ~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK);
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r |= 0x80000000 | L2C_SNP_SSR_32G | L2C_SNP_ESR;
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mtdcr(DCRN_L2C0_SNP1, r);
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asm volatile ("sync" ::: "memory");
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/* Enable ICU/DCU ports */
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r = mfdcr(DCRN_L2C0_CFG);
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r &= ~(L2C_CFG_DCW_MASK | L2C_CFG_PMUX_MASK | L2C_CFG_PMIM | L2C_CFG_TPEI
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| L2C_CFG_CPEI | L2C_CFG_NAM | L2C_CFG_NBRM);
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r |= L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_TPC | L2C_CFG_CPC | L2C_CFG_FRAN
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| L2C_CFG_CPIM | L2C_CFG_TPIM | L2C_CFG_LIM | L2C_CFG_SMCM;
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mtdcr(DCRN_L2C0_CFG, r);
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asm volatile ("sync; isync" ::: "memory");
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local_irq_restore(flags);
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}
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/* Disable L2 cache */
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void __init ibm440gx_l2c_disable(void){
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u32 r;
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unsigned long flags;
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local_irq_save(flags);
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asm volatile ("sync" ::: "memory");
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/* Disable L2C mode */
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r = mfdcr(DCRN_L2C0_CFG) & ~(L2C_CFG_L2M | L2C_CFG_ICU | L2C_CFG_DCU);
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mtdcr(DCRN_L2C0_CFG, r);
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/* Enable SRAM */
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mtdcr(DCRN_SRAM0_DPC, mfdcr(DCRN_SRAM0_DPC) | SRAM_DPC_ENABLE);
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mtdcr(DCRN_SRAM0_SB0CR,
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SRAM_SBCR_BAS0 | SRAM_SBCR_BS_64KB | SRAM_SBCR_BU_RW);
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mtdcr(DCRN_SRAM0_SB1CR,
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SRAM_SBCR_BAS1 | SRAM_SBCR_BS_64KB | SRAM_SBCR_BU_RW);
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mtdcr(DCRN_SRAM0_SB2CR,
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SRAM_SBCR_BAS2 | SRAM_SBCR_BS_64KB | SRAM_SBCR_BU_RW);
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mtdcr(DCRN_SRAM0_SB3CR,
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SRAM_SBCR_BAS3 | SRAM_SBCR_BS_64KB | SRAM_SBCR_BU_RW);
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asm volatile ("sync; isync" ::: "memory");
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local_irq_restore(flags);
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}
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void __init ibm440gx_l2c_setup(struct ibm44x_clocks* p)
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{
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/* Disable L2C on rev.A, rev.B and 800MHz version of rev.C,
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enable it on all other revisions
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*/
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if (strcmp(cur_cpu_spec->cpu_name, "440GX Rev. A") == 0 ||
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strcmp(cur_cpu_spec->cpu_name, "440GX Rev. B") == 0
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|| (strcmp(cur_cpu_spec->cpu_name, "440GX Rev. C")
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== 0 && p->cpu > 667000000))
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ibm440gx_l2c_disable();
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else
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ibm440gx_l2c_enable();
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}
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int __init ibm440gx_get_eth_grp(void)
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{
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return (SDR_READ(DCRN_SDR_PFC1) & DCRN_SDR_PFC1_EPS) >> DCRN_SDR_PFC1_EPS_SHIFT;
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}
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void __init ibm440gx_set_eth_grp(int group)
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{
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SDR_WRITE(DCRN_SDR_PFC1, (SDR_READ(DCRN_SDR_PFC1) & ~DCRN_SDR_PFC1_EPS) | (group << DCRN_SDR_PFC1_EPS_SHIFT));
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}
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void __init ibm440gx_tah_enable(void)
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{
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/* Enable TAH0 and TAH1 */
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SDR_WRITE(DCRN_SDR_MFR,SDR_READ(DCRN_SDR_MFR) &
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~DCRN_SDR_MFR_TAH0);
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SDR_WRITE(DCRN_SDR_MFR,SDR_READ(DCRN_SDR_MFR) &
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~DCRN_SDR_MFR_TAH1);
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}
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int ibm440gx_show_cpuinfo(struct seq_file *m){
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u32 l2c_cfg = mfdcr(DCRN_L2C0_CFG);
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const char* s;
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if (l2c_cfg & L2C_CFG_L2M){
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switch (l2c_cfg & (L2C_CFG_ICU | L2C_CFG_DCU)){
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case L2C_CFG_ICU: s = "I-Cache only"; break;
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case L2C_CFG_DCU: s = "D-Cache only"; break;
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default: s = "I-Cache/D-Cache"; break;
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}
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}
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else
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s = "disabled";
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seq_printf(m, "L2-Cache\t: %s (0x%08x 0x%08x)\n", s,
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l2c_cfg, mfdcr(DCRN_L2C0_SR));
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return 0;
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}
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void __init ibm440gx_platform_init(unsigned long r3, unsigned long r4,
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unsigned long r5, unsigned long r6,
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unsigned long r7)
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{
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/* Erratum 440_43 workaround, disable L1 cache parity checking */
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if (!strcmp(cur_cpu_spec->cpu_name, "440GX Rev. C") ||
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!strcmp(cur_cpu_spec->cpu_name, "440GX Rev. F"))
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mtspr(SPRN_CCR1, mfspr(SPRN_CCR1) | CCR1_DPC);
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ibm44x_platform_init(r3, r4, r5, r6, r7);
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}
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