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745 lines
19 KiB
745 lines
19 KiB
/*
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* Board setup routines for the Motorola SPS Sandpoint Test Platform.
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*
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* Author: Mark A. Greer
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* mgreer@mvista.com
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*
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* 2000-2003 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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/*
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* This file adds support for the Motorola SPS Sandpoint Test Platform.
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* These boards have a PPMC slot for the processor so any combination
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* of cpu and host bridge can be attached. This port is for an 8240 PPMC
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* module from Motorola SPS and other closely related cpu/host bridge
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* combinations (e.g., 750/755/7400 with MPC107 host bridge).
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* The sandpoint itself has a Windbond 83c553 (PCI-ISA bridge, 2 DMA ctlrs, 2
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* cascaded 8259 interrupt ctlrs, 8254 Timer/Counter, and an IDE ctlr), a
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* National 87308 (RTC, 2 UARTs, Keyboard & mouse ctlrs, and a floppy ctlr),
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* and 4 PCI slots (only 2 of which are usable; the other 2 are keyed for 3.3V
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* but are really 5V).
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*
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* The firmware on the sandpoint is called DINK (not my acronym :). This port
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* depends on DINK to do some basic initialization (e.g., initialize the memory
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* ctlr) and to ensure that the processor is using MAP B (CHRP map).
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*
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* The switch settings for the Sandpoint board MUST be as follows:
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* S3: down
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* S4: up
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* S5: up
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* S6: down
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*
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* 'down' is in the direction from the PCI slots towards the PPMC slot;
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* 'up' is in the direction from the PPMC slot towards the PCI slots.
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* Be careful, the way the sandpoint board is installed in XT chasses will
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* make the directions reversed.
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*
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* Since Motorola listened to our suggestions for improvement, we now have
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* the Sandpoint X3 board. All of the PCI slots are available, it uses
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* the serial interrupt interface (just a hardware thing we need to
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* configure properly).
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*
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* Use the default X3 switch settings. The interrupts are then:
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* EPIC Source
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* 0 SIOINT (8259, active low)
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* 1 PCI #1
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* 2 PCI #2
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* 3 PCI #3
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* 4 PCI #4
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* 7 Winbond INTC (IDE interrupt)
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* 8 Winbond INTD (IDE interrupt)
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*
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*
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* Motorola has finally released a version of DINK32 that correctly
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* (seemingly) initalizes the memory controller correctly, regardless
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* of the amount of memory in the system. Once a method of determining
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* what version of DINK initializes the system for us, if applicable, is
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* found, we can hopefully stop hardcoding 32MB of RAM.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/major.h>
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#include <linux/initrd.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/ide.h>
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#include <linux/seq_file.h>
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#include <linux/root_dev.h>
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#include <linux/serial.h>
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#include <linux/tty.h> /* for linux/serial_core.h */
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#include <linux/serial_core.h>
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#include <linux/serial_8250.h>
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#include <asm/system.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/time.h>
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#include <asm/dma.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/prom.h>
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#include <asm/smp.h>
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#include <asm/vga.h>
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#include <asm/open_pic.h>
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#include <asm/i8259.h>
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#include <asm/todc.h>
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#include <asm/bootinfo.h>
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#include <asm/mpc10x.h>
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#include <asm/pci-bridge.h>
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#include <asm/kgdb.h>
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#include <asm/ppc_sys.h>
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#include "sandpoint.h"
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/* Set non-zero if an X2 Sandpoint detected. */
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static int sandpoint_is_x2;
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unsigned char __res[sizeof(bd_t)];
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static void sandpoint_halt(void);
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static void sandpoint_probe_type(void);
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/*
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* Define all of the IRQ senses and polarities. Taken from the
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* Sandpoint X3 User's manual.
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*/
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static u_char sandpoint_openpic_initsenses[] __initdata = {
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 0: SIOINT */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 2: PCI Slot 1 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 3: PCI Slot 2 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 4: PCI Slot 3 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 5: PCI Slot 4 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 8: IDE (INT C) */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE) /* 9: IDE (INT D) */
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};
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/*
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* Motorola SPS Sandpoint interrupt routing.
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*/
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static inline int
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x3_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
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{
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static char pci_irq_table[][4] =
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/*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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{
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{ 16, 0, 0, 0 }, /* IDSEL 11 - i8259 on Winbond */
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{ 0, 0, 0, 0 }, /* IDSEL 12 - unused */
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{ 18, 21, 20, 19 }, /* IDSEL 13 - PCI slot 1 */
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{ 19, 18, 21, 20 }, /* IDSEL 14 - PCI slot 2 */
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{ 20, 19, 18, 21 }, /* IDSEL 15 - PCI slot 3 */
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{ 21, 20, 19, 18 }, /* IDSEL 16 - PCI slot 4 */
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};
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const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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}
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static inline int
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x2_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
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{
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static char pci_irq_table[][4] =
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/*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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{
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{ 18, 0, 0, 0 }, /* IDSEL 11 - i8259 on Windbond */
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{ 0, 0, 0, 0 }, /* IDSEL 12 - unused */
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{ 16, 17, 18, 19 }, /* IDSEL 13 - PCI slot 1 */
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{ 17, 18, 19, 16 }, /* IDSEL 14 - PCI slot 2 */
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{ 18, 19, 16, 17 }, /* IDSEL 15 - PCI slot 3 */
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{ 19, 16, 17, 18 }, /* IDSEL 16 - PCI slot 4 */
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};
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const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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}
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static void __init
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sandpoint_setup_winbond_83553(struct pci_controller *hose)
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{
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int devfn;
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/*
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* Route IDE interrupts directly to the 8259's IRQ 14 & 15.
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* We can't route the IDE interrupt to PCI INTC# or INTD# because those
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* woule interfere with the PMC's INTC# and INTD# lines.
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*/
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/*
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* Winbond Fcn 0
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*/
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devfn = PCI_DEVFN(11,0);
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early_write_config_byte(hose,
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0,
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devfn,
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0x43, /* IDE Interrupt Routing Control */
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0xef);
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early_write_config_word(hose,
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0,
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devfn,
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0x44, /* PCI Interrupt Routing Control */
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0x0000);
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/* Want ISA memory cycles to be forwarded to PCI bus */
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early_write_config_byte(hose,
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0,
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devfn,
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0x48, /* ISA-to-PCI Addr Decoder Control */
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0xf0);
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/* Enable Port 92. */
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early_write_config_byte(hose,
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0,
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devfn,
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0x4e, /* AT System Control Register */
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0x06);
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/*
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* Winbond Fcn 1
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*/
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devfn = PCI_DEVFN(11,1);
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/* Put IDE controller into native mode. */
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early_write_config_byte(hose,
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0,
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devfn,
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0x09, /* Programming interface Register */
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0x8f);
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/* Init IRQ routing, enable both ports, disable fast 16 */
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early_write_config_dword(hose,
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0,
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devfn,
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0x40, /* IDE Control/Status Register */
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0x00ff0011);
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return;
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}
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/* On the sandpoint X2, we must avoid sending configuration cycles to
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* device #12 (IDSEL addr = AD12).
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*/
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static int
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x2_exclude_device(u_char bus, u_char devfn)
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{
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if ((bus == 0) && (PCI_SLOT(devfn) == SANDPOINT_HOST_BRIDGE_IDSEL))
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return PCIBIOS_DEVICE_NOT_FOUND;
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else
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return PCIBIOS_SUCCESSFUL;
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}
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static void __init
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sandpoint_find_bridges(void)
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{
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struct pci_controller *hose;
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hose = pcibios_alloc_controller();
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if (!hose)
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return;
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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if (mpc10x_bridge_init(hose,
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MPC10X_MEM_MAP_B,
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MPC10X_MEM_MAP_B,
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MPC10X_MAPB_EUMB_BASE) == 0) {
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/* Do early winbond init, then scan PCI bus */
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sandpoint_setup_winbond_83553(hose);
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hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
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ppc_md.pcibios_fixup = NULL;
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ppc_md.pcibios_fixup_bus = NULL;
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ppc_md.pci_swizzle = common_swizzle;
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if (sandpoint_is_x2) {
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ppc_md.pci_map_irq = x2_map_irq;
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ppc_md.pci_exclude_device = x2_exclude_device;
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} else
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ppc_md.pci_map_irq = x3_map_irq;
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}
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else {
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if (ppc_md.progress)
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ppc_md.progress("Bridge init failed", 0x100);
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printk("Host bridge init failed\n");
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}
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return;
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}
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static void __init
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sandpoint_setup_arch(void)
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{
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/* Probe for Sandpoint model */
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sandpoint_probe_type();
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if (sandpoint_is_x2)
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epic_serial_mode = 0;
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loops_per_jiffy = 100000000 / HZ;
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#ifdef CONFIG_BLK_DEV_INITRD
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if (initrd_start)
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ROOT_DEV = Root_RAM0;
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else
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#endif
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#ifdef CONFIG_ROOT_NFS
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ROOT_DEV = Root_NFS;
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#else
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ROOT_DEV = Root_HDA1;
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#endif
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/* Lookup PCI host bridges */
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sandpoint_find_bridges();
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if (strncmp (cur_ppc_sys_spec->ppc_sys_name, "8245", 4) == 0)
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{
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bd_t *bp = (bd_t *)__res;
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struct plat_serial8250_port *pdata;
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pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART0);
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if (pdata)
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{
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pdata[0].uartclk = bp->bi_busfreq;
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}
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#ifdef CONFIG_SANDPOINT_ENABLE_UART1
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pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART1);
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if (pdata)
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{
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pdata[0].uartclk = bp->bi_busfreq;
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}
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#else
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ppc_sys_device_remove(MPC10X_UART1);
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#endif
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}
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printk(KERN_INFO "Motorola SPS Sandpoint Test Platform\n");
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printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n");
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/* DINK32 12.3 and below do not correctly enable any caches.
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* We will do this now with good known values. Future versions
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* of DINK32 are supposed to get this correct.
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*/
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if (cpu_has_feature(CPU_FTR_SPEC7450))
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/* 745x is different. We only want to pass along enable. */
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_set_L2CR(L2CR_L2E);
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else if (cpu_has_feature(CPU_FTR_L2CR))
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/* All modules have 1MB of L2. We also assume that an
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* L2 divisor of 3 will work.
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*/
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_set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3
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| L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF);
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#if 0
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/* Untested right now. */
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if (cpu_has_feature(CPU_FTR_L3CR)) {
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/* Magic value. */
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_set_L3CR(0x8f032000);
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}
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#endif
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}
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#define SANDPOINT_87308_CFG_ADDR 0x15c
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#define SANDPOINT_87308_CFG_DATA 0x15d
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#define SANDPOINT_87308_CFG_INB(addr, byte) { \
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outb((addr), SANDPOINT_87308_CFG_ADDR); \
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(byte) = inb(SANDPOINT_87308_CFG_DATA); \
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}
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#define SANDPOINT_87308_CFG_OUTB(addr, byte) { \
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outb((addr), SANDPOINT_87308_CFG_ADDR); \
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outb((byte), SANDPOINT_87308_CFG_DATA); \
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}
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#define SANDPOINT_87308_SELECT_DEV(dev_num) { \
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SANDPOINT_87308_CFG_OUTB(0x07, (dev_num)); \
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}
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#define SANDPOINT_87308_DEV_ENABLE(dev_num) { \
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SANDPOINT_87308_SELECT_DEV(dev_num); \
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SANDPOINT_87308_CFG_OUTB(0x30, 0x01); \
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}
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/*
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* To probe the Sandpoint type, we need to check for a connection between GPIO
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* pins 6 and 7 on the NS87308 SuperIO.
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*/
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static void __init sandpoint_probe_type(void)
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{
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u8 x;
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/* First, ensure that the GPIO pins are enabled. */
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SANDPOINT_87308_SELECT_DEV(0x07); /* Select GPIO logical device */
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SANDPOINT_87308_CFG_OUTB(0x60, 0x07); /* Base address 0x700 */
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SANDPOINT_87308_CFG_OUTB(0x61, 0x00);
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SANDPOINT_87308_CFG_OUTB(0x30, 0x01); /* Enable */
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/* Now, set pin 7 to output and pin 6 to input. */
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outb((inb(0x701) | 0x80) & 0xbf, 0x701);
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/* Set push-pull output */
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outb(inb(0x702) | 0x80, 0x702);
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/* Set pull-up on input */
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outb(inb(0x703) | 0x40, 0x703);
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/* Set output high and check */
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x = inb(0x700);
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outb(x | 0x80, 0x700);
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x = inb(0x700);
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sandpoint_is_x2 = ! (x & 0x40);
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if (ppc_md.progress && sandpoint_is_x2)
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ppc_md.progress("High output says X2", 0);
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/* Set output low and check */
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outb(x & 0x7f, 0x700);
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sandpoint_is_x2 |= inb(0x700) & 0x40;
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if (ppc_md.progress && sandpoint_is_x2)
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ppc_md.progress("Low output says X2", 0);
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if (ppc_md.progress && ! sandpoint_is_x2)
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ppc_md.progress("Sandpoint is X3", 0);
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}
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/*
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* Fix IDE interrupts.
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*/
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static int __init
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sandpoint_fix_winbond_83553(void)
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{
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/* Make some 8259 interrupt level sensitive */
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outb(0xe0, 0x4d0);
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outb(0xde, 0x4d1);
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return 0;
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}
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arch_initcall(sandpoint_fix_winbond_83553);
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/*
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* Initialize the ISA devices on the Nat'l PC87308VUL SuperIO chip.
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*/
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static int __init
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sandpoint_setup_natl_87308(void)
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{
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u_char reg;
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/*
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* Enable all the devices on the Super I/O chip.
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*/
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SANDPOINT_87308_SELECT_DEV(0x00); /* Select kbd logical device */
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SANDPOINT_87308_CFG_OUTB(0xf0, 0x00); /* Set KBC clock to 8 Mhz */
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SANDPOINT_87308_DEV_ENABLE(0x00); /* Enable keyboard */
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SANDPOINT_87308_DEV_ENABLE(0x01); /* Enable mouse */
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SANDPOINT_87308_DEV_ENABLE(0x02); /* Enable rtc */
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SANDPOINT_87308_DEV_ENABLE(0x03); /* Enable fdc (floppy) */
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SANDPOINT_87308_DEV_ENABLE(0x04); /* Enable parallel */
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SANDPOINT_87308_DEV_ENABLE(0x05); /* Enable UART 2 */
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SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */
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SANDPOINT_87308_DEV_ENABLE(0x06); /* Enable UART 1 */
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SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */
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/* Set up floppy in PS/2 mode */
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outb(0x09, SIO_CONFIG_RA);
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reg = inb(SIO_CONFIG_RD);
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reg = (reg & 0x3F) | 0x40;
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outb(reg, SIO_CONFIG_RD);
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outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */
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return 0;
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}
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arch_initcall(sandpoint_setup_natl_87308);
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static int __init
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sandpoint_request_io(void)
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{
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request_region(0x00,0x20,"dma1");
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request_region(0x20,0x20,"pic1");
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request_region(0x40,0x20,"timer");
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request_region(0x80,0x10,"dma page reg");
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request_region(0xa0,0x20,"pic2");
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request_region(0xc0,0x20,"dma2");
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return 0;
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}
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arch_initcall(sandpoint_request_io);
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|
|
/*
|
|
* Interrupt setup and service. Interrrupts on the Sandpoint come
|
|
* from the four PCI slots plus the 8259 in the Winbond Super I/O (SIO).
|
|
* The 8259 is cascaded from EPIC IRQ0, IRQ1-4 map to PCI slots 1-4,
|
|
* IDE is on EPIC 7 and 8.
|
|
*/
|
|
static void __init
|
|
sandpoint_init_IRQ(void)
|
|
{
|
|
int i;
|
|
|
|
OpenPIC_InitSenses = sandpoint_openpic_initsenses;
|
|
OpenPIC_NumInitSenses = sizeof(sandpoint_openpic_initsenses);
|
|
|
|
mpc10x_set_openpic();
|
|
openpic_hookup_cascade(sandpoint_is_x2 ? 17 : NUM_8259_INTERRUPTS, "82c59 cascade",
|
|
i8259_irq);
|
|
|
|
/*
|
|
* The EPIC allows for a read in the range of 0xFEF00000 ->
|
|
* 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction.
|
|
*/
|
|
i8259_init(0xfef00000, 0);
|
|
}
|
|
|
|
static unsigned long __init
|
|
sandpoint_find_end_of_memory(void)
|
|
{
|
|
bd_t *bp = (bd_t *)__res;
|
|
|
|
if (bp->bi_memsize)
|
|
return bp->bi_memsize;
|
|
|
|
/* DINK32 13.0 correctly initalizes things, so iff you use
|
|
* this you _should_ be able to change this instead of a
|
|
* hardcoded value. */
|
|
#if 0
|
|
return mpc10x_get_mem_size(MPC10X_MEM_MAP_B);
|
|
#else
|
|
return 32*1024*1024;
|
|
#endif
|
|
}
|
|
|
|
static void __init
|
|
sandpoint_map_io(void)
|
|
{
|
|
io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
|
|
}
|
|
|
|
static void
|
|
sandpoint_restart(char *cmd)
|
|
{
|
|
local_irq_disable();
|
|
|
|
/* Set exception prefix high - to the firmware */
|
|
_nmask_and_or_msr(0, MSR_IP);
|
|
|
|
/* Reset system via Port 92 */
|
|
outb(0x00, 0x92);
|
|
outb(0x01, 0x92);
|
|
for(;;); /* Spin until reset happens */
|
|
}
|
|
|
|
static void
|
|
sandpoint_power_off(void)
|
|
{
|
|
local_irq_disable();
|
|
for(;;); /* No way to shut power off with software */
|
|
/* NOTREACHED */
|
|
}
|
|
|
|
static void
|
|
sandpoint_halt(void)
|
|
{
|
|
sandpoint_power_off();
|
|
/* NOTREACHED */
|
|
}
|
|
|
|
static int
|
|
sandpoint_show_cpuinfo(struct seq_file *m)
|
|
{
|
|
seq_printf(m, "vendor\t\t: Motorola SPS\n");
|
|
seq_printf(m, "machine\t\t: Sandpoint\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
|
|
/*
|
|
* IDE support.
|
|
*/
|
|
static int sandpoint_ide_ports_known = 0;
|
|
static unsigned long sandpoint_ide_regbase[MAX_HWIFS];
|
|
static unsigned long sandpoint_ide_ctl_regbase[MAX_HWIFS];
|
|
static unsigned long sandpoint_idedma_regbase;
|
|
|
|
static void
|
|
sandpoint_ide_probe(void)
|
|
{
|
|
struct pci_dev *pdev = pci_get_device(PCI_VENDOR_ID_WINBOND,
|
|
PCI_DEVICE_ID_WINBOND_82C105, NULL);
|
|
|
|
if (pdev) {
|
|
sandpoint_ide_regbase[0]=pdev->resource[0].start;
|
|
sandpoint_ide_regbase[1]=pdev->resource[2].start;
|
|
sandpoint_ide_ctl_regbase[0]=pdev->resource[1].start;
|
|
sandpoint_ide_ctl_regbase[1]=pdev->resource[3].start;
|
|
sandpoint_idedma_regbase=pdev->resource[4].start;
|
|
pci_dev_put(pdev);
|
|
}
|
|
|
|
sandpoint_ide_ports_known = 1;
|
|
}
|
|
|
|
static int
|
|
sandpoint_ide_default_irq(unsigned long base)
|
|
{
|
|
if (sandpoint_ide_ports_known == 0)
|
|
sandpoint_ide_probe();
|
|
|
|
if (base == sandpoint_ide_regbase[0])
|
|
return SANDPOINT_IDE_INT0;
|
|
else if (base == sandpoint_ide_regbase[1])
|
|
return SANDPOINT_IDE_INT1;
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
static unsigned long
|
|
sandpoint_ide_default_io_base(int index)
|
|
{
|
|
if (sandpoint_ide_ports_known == 0)
|
|
sandpoint_ide_probe();
|
|
|
|
return sandpoint_ide_regbase[index];
|
|
}
|
|
|
|
static void __init
|
|
sandpoint_ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port,
|
|
unsigned long ctrl_port, int *irq)
|
|
{
|
|
unsigned long reg = data_port;
|
|
uint alt_status_base;
|
|
int i;
|
|
|
|
for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
|
|
hw->io_ports[i] = reg++;
|
|
}
|
|
|
|
if (data_port == sandpoint_ide_regbase[0]) {
|
|
alt_status_base = sandpoint_ide_ctl_regbase[0] + 2;
|
|
hw->irq = 14;
|
|
}
|
|
else if (data_port == sandpoint_ide_regbase[1]) {
|
|
alt_status_base = sandpoint_ide_ctl_regbase[1] + 2;
|
|
hw->irq = 15;
|
|
}
|
|
else {
|
|
alt_status_base = 0;
|
|
hw->irq = 0;
|
|
}
|
|
|
|
if (ctrl_port) {
|
|
hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
|
|
} else {
|
|
hw->io_ports[IDE_CONTROL_OFFSET] = alt_status_base;
|
|
}
|
|
|
|
if (irq != NULL) {
|
|
*irq = hw->irq;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Set BAT 3 to map 0xf8000000 to end of physical memory space 1-to-1.
|
|
*/
|
|
static __inline__ void
|
|
sandpoint_set_bat(void)
|
|
{
|
|
unsigned long bat3u, bat3l;
|
|
|
|
__asm__ __volatile__(
|
|
" lis %0,0xf800\n \
|
|
ori %1,%0,0x002a\n \
|
|
ori %0,%0,0x0ffe\n \
|
|
mtspr 0x21e,%0\n \
|
|
mtspr 0x21f,%1\n \
|
|
isync\n \
|
|
sync "
|
|
: "=r" (bat3u), "=r" (bat3l));
|
|
}
|
|
|
|
TODC_ALLOC();
|
|
|
|
void __init
|
|
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
|
unsigned long r6, unsigned long r7)
|
|
{
|
|
parse_bootinfo(find_bootinfo());
|
|
|
|
/* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer)
|
|
* are non-zero, then we should use the board info from the bd_t
|
|
* structure and the cmdline pointed to by r6 instead of the
|
|
* information from birecs, if any. Otherwise, use the information
|
|
* from birecs as discovered by the preceeding call to
|
|
* parse_bootinfo(). This rule should work with both PPCBoot, which
|
|
* uses a bd_t board info structure, and the kernel boot wrapper,
|
|
* which uses birecs.
|
|
*/
|
|
if (r3 && r6) {
|
|
/* copy board info structure */
|
|
memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
|
|
/* copy command line */
|
|
*(char *)(r7+KERNELBASE) = 0;
|
|
strcpy(cmd_line, (char *)(r6+KERNELBASE));
|
|
}
|
|
|
|
#ifdef CONFIG_BLK_DEV_INITRD
|
|
/* take care of initrd if we have one */
|
|
if (r4) {
|
|
initrd_start = r4 + KERNELBASE;
|
|
initrd_end = r5 + KERNELBASE;
|
|
}
|
|
#endif /* CONFIG_BLK_DEV_INITRD */
|
|
|
|
/* Map in board regs, etc. */
|
|
sandpoint_set_bat();
|
|
|
|
isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
|
|
isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
|
|
pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
|
|
ISA_DMA_THRESHOLD = 0x00ffffff;
|
|
DMA_MODE_READ = 0x44;
|
|
DMA_MODE_WRITE = 0x48;
|
|
ppc_do_canonicalize_irqs = 1;
|
|
|
|
ppc_md.setup_arch = sandpoint_setup_arch;
|
|
ppc_md.show_cpuinfo = sandpoint_show_cpuinfo;
|
|
ppc_md.init_IRQ = sandpoint_init_IRQ;
|
|
ppc_md.get_irq = openpic_get_irq;
|
|
|
|
ppc_md.restart = sandpoint_restart;
|
|
ppc_md.power_off = sandpoint_power_off;
|
|
ppc_md.halt = sandpoint_halt;
|
|
|
|
ppc_md.find_end_of_memory = sandpoint_find_end_of_memory;
|
|
ppc_md.setup_io_mappings = sandpoint_map_io;
|
|
|
|
TODC_INIT(TODC_TYPE_PC97307, 0x70, 0x00, 0x71, 8);
|
|
ppc_md.time_init = todc_time_init;
|
|
ppc_md.set_rtc_time = todc_set_rtc_time;
|
|
ppc_md.get_rtc_time = todc_get_rtc_time;
|
|
ppc_md.calibrate_decr = todc_calibrate_decr;
|
|
|
|
ppc_md.nvram_read_val = todc_mc146818_read_val;
|
|
ppc_md.nvram_write_val = todc_mc146818_write_val;
|
|
|
|
#ifdef CONFIG_KGDB
|
|
ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
|
|
#endif
|
|
#ifdef CONFIG_SERIAL_TEXT_DEBUG
|
|
ppc_md.progress = gen550_progress;
|
|
#endif
|
|
|
|
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
|
|
ppc_ide_md.default_irq = sandpoint_ide_default_irq;
|
|
ppc_ide_md.default_io_base = sandpoint_ide_default_io_base;
|
|
ppc_ide_md.ide_init_hwif = sandpoint_ide_init_hwif_ports;
|
|
#endif
|
|
}
|
|
|