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429 lines
9.8 KiB
429 lines
9.8 KiB
/*
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* Copyright 2007, Michael Ellerman, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/msi.h>
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#include <linux/reboot.h>
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#include <asm/dcr.h>
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#include <asm/machdep.h>
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#include <asm/prom.h>
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/*
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* MSIC registers, specified as offsets from dcr_base
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*/
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#define MSIC_CTRL_REG 0x0
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/* Base Address registers specify FIFO location in BE memory */
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#define MSIC_BASE_ADDR_HI_REG 0x3
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#define MSIC_BASE_ADDR_LO_REG 0x4
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/* Hold the read/write offsets into the FIFO */
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#define MSIC_READ_OFFSET_REG 0x5
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#define MSIC_WRITE_OFFSET_REG 0x6
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/* MSIC control register flags */
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#define MSIC_CTRL_ENABLE 0x0001
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#define MSIC_CTRL_FIFO_FULL_ENABLE 0x0002
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#define MSIC_CTRL_IRQ_ENABLE 0x0008
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#define MSIC_CTRL_FULL_STOP_ENABLE 0x0010
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/*
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* The MSIC can be configured to use a FIFO of 32KB, 64KB, 128KB or 256KB.
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* Currently we're using a 64KB FIFO size.
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*/
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#define MSIC_FIFO_SIZE_SHIFT 16
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#define MSIC_FIFO_SIZE_BYTES (1 << MSIC_FIFO_SIZE_SHIFT)
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/*
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* To configure the FIFO size as (1 << n) bytes, we write (n - 15) into bits
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* 8-9 of the MSIC control reg.
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*/
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#define MSIC_CTRL_FIFO_SIZE (((MSIC_FIFO_SIZE_SHIFT - 15) << 8) & 0x300)
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/*
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* We need to mask the read/write offsets to make sure they stay within
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* the bounds of the FIFO. Also they should always be 16-byte aligned.
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*/
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#define MSIC_FIFO_SIZE_MASK ((MSIC_FIFO_SIZE_BYTES - 1) & ~0xFu)
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/* Each entry in the FIFO is 16 bytes, the first 4 bytes hold the irq # */
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#define MSIC_FIFO_ENTRY_SIZE 0x10
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struct axon_msic {
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struct irq_host *irq_host;
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__le32 *fifo;
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dcr_host_t dcr_host;
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struct list_head list;
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u32 read_offset;
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};
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static LIST_HEAD(axon_msic_list);
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static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val)
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{
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pr_debug("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n);
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dcr_write(msic->dcr_host, dcr_n, val);
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}
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static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
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{
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struct axon_msic *msic = get_irq_data(irq);
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u32 write_offset, msi;
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int idx;
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write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG);
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pr_debug("axon_msi: original write_offset 0x%x\n", write_offset);
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/* write_offset doesn't wrap properly, so we have to mask it */
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write_offset &= MSIC_FIFO_SIZE_MASK;
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while (msic->read_offset != write_offset) {
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idx = msic->read_offset / sizeof(__le32);
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msi = le32_to_cpu(msic->fifo[idx]);
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msi &= 0xFFFF;
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pr_debug("axon_msi: woff %x roff %x msi %x\n",
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write_offset, msic->read_offset, msi);
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msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
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msic->read_offset &= MSIC_FIFO_SIZE_MASK;
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if (msi < NR_IRQS && irq_map[msi].host == msic->irq_host)
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generic_handle_irq(msi);
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else
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pr_debug("axon_msi: invalid irq 0x%x!\n", msi);
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}
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desc->chip->eoi(irq);
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}
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static struct axon_msic *find_msi_translator(struct pci_dev *dev)
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{
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struct irq_host *irq_host;
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struct device_node *dn, *tmp;
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const phandle *ph;
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struct axon_msic *msic = NULL;
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dn = of_node_get(pci_device_to_OF_node(dev));
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if (!dn) {
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dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
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return NULL;
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}
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for (; dn; tmp = of_get_parent(dn), of_node_put(dn), dn = tmp) {
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ph = of_get_property(dn, "msi-translator", NULL);
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if (ph)
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break;
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}
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if (!ph) {
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dev_dbg(&dev->dev,
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"axon_msi: no msi-translator property found\n");
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goto out_error;
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}
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tmp = dn;
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dn = of_find_node_by_phandle(*ph);
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if (!dn) {
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dev_dbg(&dev->dev,
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"axon_msi: msi-translator doesn't point to a node\n");
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goto out_error;
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}
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irq_host = irq_find_host(dn);
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if (!irq_host) {
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dev_dbg(&dev->dev, "axon_msi: no irq_host found for node %s\n",
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dn->full_name);
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goto out_error;
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}
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msic = irq_host->host_data;
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out_error:
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of_node_put(dn);
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of_node_put(tmp);
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return msic;
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}
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static int axon_msi_check_device(struct pci_dev *dev, int nvec, int type)
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{
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if (!find_msi_translator(dev))
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return -ENODEV;
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return 0;
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}
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static int setup_msi_msg_address(struct pci_dev *dev, struct msi_msg *msg)
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{
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struct device_node *dn, *tmp;
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struct msi_desc *entry;
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int len;
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const u32 *prop;
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dn = of_node_get(pci_device_to_OF_node(dev));
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if (!dn) {
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dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
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return -ENODEV;
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}
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entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
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for (; dn; tmp = of_get_parent(dn), of_node_put(dn), dn = tmp) {
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if (entry->msi_attrib.is_64) {
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prop = of_get_property(dn, "msi-address-64", &len);
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if (prop)
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break;
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}
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prop = of_get_property(dn, "msi-address-32", &len);
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if (prop)
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break;
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}
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if (!prop) {
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dev_dbg(&dev->dev,
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"axon_msi: no msi-address-(32|64) properties found\n");
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return -ENOENT;
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}
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switch (len) {
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case 8:
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msg->address_hi = prop[0];
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msg->address_lo = prop[1];
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break;
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case 4:
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msg->address_hi = 0;
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msg->address_lo = prop[0];
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break;
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default:
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dev_dbg(&dev->dev,
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"axon_msi: malformed msi-address-(32|64) property\n");
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of_node_put(dn);
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return -EINVAL;
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}
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of_node_put(dn);
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return 0;
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}
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static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
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{
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unsigned int virq, rc;
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struct msi_desc *entry;
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struct msi_msg msg;
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struct axon_msic *msic;
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msic = find_msi_translator(dev);
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if (!msic)
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return -ENODEV;
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rc = setup_msi_msg_address(dev, &msg);
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if (rc)
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return rc;
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/* We rely on being able to stash a virq in a u16 */
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BUILD_BUG_ON(NR_IRQS > 65536);
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list_for_each_entry(entry, &dev->msi_list, list) {
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virq = irq_create_direct_mapping(msic->irq_host);
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if (virq == NO_IRQ) {
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dev_warn(&dev->dev,
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"axon_msi: virq allocation failed!\n");
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return -1;
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}
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dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq);
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set_irq_msi(virq, entry);
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msg.data = virq;
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write_msi_msg(virq, &msg);
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}
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return 0;
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}
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static void axon_msi_teardown_msi_irqs(struct pci_dev *dev)
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{
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struct msi_desc *entry;
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dev_dbg(&dev->dev, "axon_msi: tearing down msi irqs\n");
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list_for_each_entry(entry, &dev->msi_list, list) {
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if (entry->irq == NO_IRQ)
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continue;
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set_irq_msi(entry->irq, NULL);
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irq_dispose_mapping(entry->irq);
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}
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}
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static struct irq_chip msic_irq_chip = {
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.mask = mask_msi_irq,
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.unmask = unmask_msi_irq,
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.shutdown = unmask_msi_irq,
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.typename = "AXON-MSI",
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};
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static int msic_host_map(struct irq_host *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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set_irq_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq);
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return 0;
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}
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static struct irq_host_ops msic_host_ops = {
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.map = msic_host_map,
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};
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static int axon_msi_notify_reboot(struct notifier_block *nb,
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unsigned long code, void *data)
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{
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struct axon_msic *msic;
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u32 tmp;
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list_for_each_entry(msic, &axon_msic_list, list) {
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pr_debug("axon_msi: disabling %s\n",
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msic->irq_host->of_node->full_name);
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tmp = dcr_read(msic->dcr_host, MSIC_CTRL_REG);
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tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE;
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msic_dcr_write(msic, MSIC_CTRL_REG, tmp);
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}
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return 0;
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}
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static struct notifier_block axon_msi_reboot_notifier = {
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.notifier_call = axon_msi_notify_reboot
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};
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static int axon_msi_setup_one(struct device_node *dn)
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{
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struct page *page;
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struct axon_msic *msic;
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unsigned int virq;
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int dcr_base, dcr_len;
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pr_debug("axon_msi: setting up dn %s\n", dn->full_name);
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msic = kzalloc(sizeof(struct axon_msic), GFP_KERNEL);
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if (!msic) {
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printk(KERN_ERR "axon_msi: couldn't allocate msic for %s\n",
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dn->full_name);
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goto out;
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}
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dcr_base = dcr_resource_start(dn, 0);
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dcr_len = dcr_resource_len(dn, 0);
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if (dcr_base == 0 || dcr_len == 0) {
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printk(KERN_ERR
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"axon_msi: couldn't parse dcr properties on %s\n",
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dn->full_name);
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goto out;
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}
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msic->dcr_host = dcr_map(dn, dcr_base, dcr_len);
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if (!DCR_MAP_OK(msic->dcr_host)) {
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printk(KERN_ERR "axon_msi: dcr_map failed for %s\n",
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dn->full_name);
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goto out_free_msic;
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}
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page = alloc_pages_node(of_node_to_nid(dn), GFP_KERNEL,
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get_order(MSIC_FIFO_SIZE_BYTES));
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if (!page) {
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printk(KERN_ERR "axon_msi: couldn't allocate fifo for %s\n",
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dn->full_name);
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goto out_free_msic;
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}
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msic->fifo = page_address(page);
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msic->irq_host = irq_alloc_host(of_node_get(dn), IRQ_HOST_MAP_NOMAP,
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NR_IRQS, &msic_host_ops, 0);
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if (!msic->irq_host) {
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printk(KERN_ERR "axon_msi: couldn't allocate irq_host for %s\n",
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dn->full_name);
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goto out_free_fifo;
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}
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msic->irq_host->host_data = msic;
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virq = irq_of_parse_and_map(dn, 0);
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if (virq == NO_IRQ) {
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printk(KERN_ERR "axon_msi: irq parse and map failed for %s\n",
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dn->full_name);
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goto out_free_host;
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}
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set_irq_data(virq, msic);
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set_irq_chained_handler(virq, axon_msi_cascade);
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pr_debug("axon_msi: irq 0x%x setup for axon_msi\n", virq);
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/* Enable the MSIC hardware */
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msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, (u64)msic->fifo >> 32);
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msic_dcr_write(msic, MSIC_BASE_ADDR_LO_REG,
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(u64)msic->fifo & 0xFFFFFFFF);
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msic_dcr_write(msic, MSIC_CTRL_REG,
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MSIC_CTRL_IRQ_ENABLE | MSIC_CTRL_ENABLE |
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MSIC_CTRL_FIFO_SIZE);
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list_add(&msic->list, &axon_msic_list);
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printk(KERN_DEBUG "axon_msi: setup MSIC on %s\n", dn->full_name);
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return 0;
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out_free_host:
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kfree(msic->irq_host);
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out_free_fifo:
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__free_pages(virt_to_page(msic->fifo), get_order(MSIC_FIFO_SIZE_BYTES));
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out_free_msic:
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kfree(msic);
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out:
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return -1;
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}
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static int axon_msi_init(void)
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{
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struct device_node *dn;
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int found = 0;
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pr_debug("axon_msi: initialising ...\n");
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for_each_compatible_node(dn, NULL, "ibm,axon-msic") {
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if (axon_msi_setup_one(dn) == 0)
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found++;
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}
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if (found) {
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ppc_md.setup_msi_irqs = axon_msi_setup_msi_irqs;
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ppc_md.teardown_msi_irqs = axon_msi_teardown_msi_irqs;
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ppc_md.msi_check_device = axon_msi_check_device;
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register_reboot_notifier(&axon_msi_reboot_notifier);
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pr_debug("axon_msi: registered callbacks!\n");
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}
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return 0;
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}
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arch_initcall(axon_msi_init);
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