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106 lines
3.4 KiB
106 lines
3.4 KiB
/*******************************************************************************
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Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 2 of the License, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc., 59
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Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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The full GNU General Public License is included in this distribution in the
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file called LICENSE.
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Contact Information:
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Linux NICS <linux.nics@intel.com>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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#ifndef _IXGB_EE_H_
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#define _IXGB_EE_H_
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#define IXGB_EEPROM_SIZE 64 /* Size in words */
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#define IXGB_ETH_LENGTH_OF_ADDRESS 6
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/* EEPROM Commands */
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#define EEPROM_READ_OPCODE 0x6 /* EERPOM read opcode */
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#define EEPROM_WRITE_OPCODE 0x5 /* EERPOM write opcode */
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#define EEPROM_ERASE_OPCODE 0x7 /* EERPOM erase opcode */
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#define EEPROM_EWEN_OPCODE 0x13 /* EERPOM erase/write enable */
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#define EEPROM_EWDS_OPCODE 0x10 /* EERPOM erast/write disable */
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/* EEPROM MAP (Word Offsets) */
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#define EEPROM_IA_1_2_REG 0x0000
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#define EEPROM_IA_3_4_REG 0x0001
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#define EEPROM_IA_5_6_REG 0x0002
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#define EEPROM_COMPATIBILITY_REG 0x0003
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#define EEPROM_PBA_1_2_REG 0x0008
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#define EEPROM_PBA_3_4_REG 0x0009
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#define EEPROM_INIT_CONTROL1_REG 0x000A
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#define EEPROM_SUBSYS_ID_REG 0x000B
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#define EEPROM_SUBVEND_ID_REG 0x000C
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#define EEPROM_DEVICE_ID_REG 0x000D
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#define EEPROM_VENDOR_ID_REG 0x000E
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#define EEPROM_INIT_CONTROL2_REG 0x000F
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#define EEPROM_SWDPINS_REG 0x0020
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#define EEPROM_CIRCUIT_CTRL_REG 0x0021
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#define EEPROM_D0_D3_POWER_REG 0x0022
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#define EEPROM_FLASH_VERSION 0x0032
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#define EEPROM_CHECKSUM_REG 0x003F
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/* Mask bits for fields in Word 0x0a of the EEPROM */
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#define EEPROM_ICW1_SIGNATURE_MASK 0xC000
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#define EEPROM_ICW1_SIGNATURE_VALID 0x4000
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#define EEPROM_ICW1_SIGNATURE_CLEAR 0x0000
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/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
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#define EEPROM_SUM 0xBABA
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/* EEPROM Map Sizes (Byte Counts) */
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#define PBA_SIZE 4
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/* EEPROM Map defines (WORD OFFSETS)*/
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/* EEPROM structure */
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struct ixgb_ee_map_type {
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uint8_t mac_addr[IXGB_ETH_LENGTH_OF_ADDRESS];
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uint16_t compatibility;
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uint16_t reserved1[4];
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uint32_t pba_number;
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uint16_t init_ctrl_reg_1;
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uint16_t subsystem_id;
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uint16_t subvendor_id;
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uint16_t device_id;
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uint16_t vendor_id;
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uint16_t init_ctrl_reg_2;
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uint16_t oem_reserved[16];
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uint16_t swdpins_reg;
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uint16_t circuit_ctrl_reg;
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uint8_t d3_power;
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uint8_t d0_power;
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uint16_t reserved2[28];
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uint16_t checksum;
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};
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/* EEPROM Functions */
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uint16_t ixgb_read_eeprom(struct ixgb_hw *hw, uint16_t reg);
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boolean_t ixgb_validate_eeprom_checksum(struct ixgb_hw *hw);
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void ixgb_update_eeprom_checksum(struct ixgb_hw *hw);
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void ixgb_write_eeprom(struct ixgb_hw *hw, uint16_t reg, uint16_t data);
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#endif /* IXGB_EE_H */
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