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101 lines
3.0 KiB
101 lines
3.0 KiB
#
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# MN10300 CPU cache options
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#
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choice
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prompt "CPU Caching mode"
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default MN10300_CACHE_WBACK
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help
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This option determines the caching mode for the kernel.
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Write-Back caching mode involves the all reads and writes causing
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the affected cacheline to be read into the cache first before being
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operated upon. Memory is not then updated by a write until the cache
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is filled and a cacheline needs to be displaced from the cache to
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make room. Only at that point is it written back.
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Write-Through caching only fetches cachelines from memory on a
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read. Writes always get written directly to memory. If the affected
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cacheline is also in cache, it will be updated too.
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The final option is to turn of caching entirely.
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config MN10300_CACHE_WBACK
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bool "Write-Back"
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help
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The dcache operates in delayed write-back mode. It must be manually
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flushed if writes are made that subsequently need to be executed or
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to be DMA'd by a device.
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config MN10300_CACHE_WTHRU
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bool "Write-Through"
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help
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The dcache operates in immediate write-through mode. Writes are
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committed to RAM immediately in addition to being stored in the
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cache. This means that the written data is immediately available for
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execution or DMA.
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This is not available for use with an SMP kernel if cache flushing
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and invalidation by automatic purge register is not selected.
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config MN10300_CACHE_DISABLED
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bool "Disabled"
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help
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The icache and dcache are disabled.
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endchoice
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config MN10300_CACHE_ENABLED
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def_bool y if !MN10300_CACHE_DISABLED
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choice
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prompt "CPU cache flush/invalidate method"
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default MN10300_CACHE_MANAGE_BY_TAG if !AM34_2
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default MN10300_CACHE_MANAGE_BY_REG if AM34_2
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depends on MN10300_CACHE_ENABLED
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help
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This determines the method by which CPU cache flushing and
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invalidation is performed.
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config MN10300_CACHE_MANAGE_BY_TAG
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bool "Use the cache tag registers directly"
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depends on !(SMP && MN10300_CACHE_WTHRU)
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config MN10300_CACHE_MANAGE_BY_REG
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bool "Flush areas by way of automatic purge registers (AM34 only)"
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depends on AM34_2
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endchoice
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config MN10300_CACHE_INV_BY_TAG
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def_bool y if MN10300_CACHE_MANAGE_BY_TAG && MN10300_CACHE_ENABLED
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config MN10300_CACHE_INV_BY_REG
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def_bool y if MN10300_CACHE_MANAGE_BY_REG && MN10300_CACHE_ENABLED
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config MN10300_CACHE_FLUSH_BY_TAG
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def_bool y if MN10300_CACHE_MANAGE_BY_TAG && MN10300_CACHE_WBACK
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config MN10300_CACHE_FLUSH_BY_REG
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def_bool y if MN10300_CACHE_MANAGE_BY_REG && MN10300_CACHE_WBACK
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config MN10300_HAS_CACHE_SNOOP
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def_bool n
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config MN10300_CACHE_SNOOP
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bool "Use CPU Cache Snooping"
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depends on MN10300_CACHE_ENABLED && MN10300_HAS_CACHE_SNOOP
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default y
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config MN10300_CACHE_FLUSH_ICACHE
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def_bool y if MN10300_CACHE_WBACK && !MN10300_CACHE_SNOOP
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help
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Set if we need the dcache flushing before the icache is invalidated.
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config MN10300_CACHE_INV_ICACHE
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def_bool y if MN10300_CACHE_WTHRU && !MN10300_CACHE_SNOOP
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help
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Set if we need the icache to be invalidated, even if the dcache is in
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write-through mode and doesn't need flushing.
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