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376 lines
9.3 KiB
376 lines
9.3 KiB
/*
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* Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
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*
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* This file contains the lowest level x86-specific interrupt
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* entry, irq-stacks and irq statistics code. All the remaining
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* irq logic is done by the generic kernel/irq/ code and
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* by the x86-specific irq controller code. (e.g. i8259.c and
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* io_apic.c.)
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*/
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#include <linux/module.h>
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#include <linux/seq_file.h>
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#include <linux/interrupt.h>
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#include <linux/kernel_stat.h>
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#include <linux/notifier.h>
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#include <linux/cpu.h>
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#include <linux/delay.h>
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#include <asm/apic.h>
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#include <asm/uaccess.h>
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DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
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EXPORT_PER_CPU_SYMBOL(irq_stat);
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DEFINE_PER_CPU(struct pt_regs *, irq_regs);
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EXPORT_PER_CPU_SYMBOL(irq_regs);
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/*
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* 'what should we do if we get a hw irq event on an illegal vector'.
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* each architecture has to answer this themselves.
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*/
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void ack_bad_irq(unsigned int irq)
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{
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printk(KERN_ERR "unexpected IRQ trap at vector %02x\n", irq);
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#ifdef CONFIG_X86_LOCAL_APIC
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/*
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* Currently unexpected vectors happen only on SMP and APIC.
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* We _must_ ack these because every local APIC has only N
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* irq slots per priority level, and a 'hanging, unacked' IRQ
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* holds up an irq slot - in excessive cases (when multiple
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* unexpected vectors occur) that might lock up the APIC
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* completely.
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* But only ack when the APIC is enabled -AK
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*/
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if (cpu_has_apic)
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ack_APIC_irq();
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#endif
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}
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#ifdef CONFIG_4KSTACKS
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/*
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* per-CPU IRQ handling contexts (thread information and stack)
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*/
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union irq_ctx {
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struct thread_info tinfo;
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u32 stack[THREAD_SIZE/sizeof(u32)];
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};
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static union irq_ctx *hardirq_ctx[NR_CPUS] __read_mostly;
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static union irq_ctx *softirq_ctx[NR_CPUS] __read_mostly;
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#endif
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/*
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* do_IRQ handles all normal device IRQ's (the special
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* SMP cross-CPU interrupts have their own specific
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* handlers).
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*/
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unsigned int do_IRQ(struct pt_regs *regs)
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{
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struct pt_regs *old_regs;
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/* high bit used in ret_from_ code */
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int irq = ~regs->orig_ax;
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struct irq_desc *desc = irq_desc + irq;
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#ifdef CONFIG_4KSTACKS
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union irq_ctx *curctx, *irqctx;
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u32 *isp;
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#endif
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if (unlikely((unsigned)irq >= NR_IRQS)) {
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printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
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__FUNCTION__, irq);
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BUG();
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}
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old_regs = set_irq_regs(regs);
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irq_enter();
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#ifdef CONFIG_DEBUG_STACKOVERFLOW
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/* Debugging check for stack overflow: is there less than 1KB free? */
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{
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long sp;
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__asm__ __volatile__("andl %%esp,%0" :
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"=r" (sp) : "0" (THREAD_SIZE - 1));
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if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) {
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printk("do_IRQ: stack overflow: %ld\n",
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sp - sizeof(struct thread_info));
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dump_stack();
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}
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}
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#endif
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#ifdef CONFIG_4KSTACKS
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curctx = (union irq_ctx *) current_thread_info();
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irqctx = hardirq_ctx[smp_processor_id()];
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/*
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* this is where we switch to the IRQ stack. However, if we are
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* already using the IRQ stack (because we interrupted a hardirq
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* handler) we can't do that and just have to keep using the
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* current stack (which is the irq stack already after all)
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*/
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if (curctx != irqctx) {
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int arg1, arg2, bx;
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/* build the stack frame on the IRQ stack */
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isp = (u32*) ((char*)irqctx + sizeof(*irqctx));
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irqctx->tinfo.task = curctx->tinfo.task;
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irqctx->tinfo.previous_esp = current_stack_pointer;
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/*
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* Copy the softirq bits in preempt_count so that the
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* softirq checks work in the hardirq context.
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*/
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irqctx->tinfo.preempt_count =
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(irqctx->tinfo.preempt_count & ~SOFTIRQ_MASK) |
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(curctx->tinfo.preempt_count & SOFTIRQ_MASK);
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asm volatile(
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" xchgl %%ebx,%%esp \n"
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" call *%%edi \n"
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" movl %%ebx,%%esp \n"
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: "=a" (arg1), "=d" (arg2), "=b" (bx)
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: "0" (irq), "1" (desc), "2" (isp),
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"D" (desc->handle_irq)
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: "memory", "cc"
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);
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} else
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#endif
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desc->handle_irq(irq, desc);
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irq_exit();
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set_irq_regs(old_regs);
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return 1;
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}
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#ifdef CONFIG_4KSTACKS
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static char softirq_stack[NR_CPUS * THREAD_SIZE]
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__attribute__((__section__(".bss.page_aligned")));
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static char hardirq_stack[NR_CPUS * THREAD_SIZE]
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__attribute__((__section__(".bss.page_aligned")));
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/*
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* allocate per-cpu stacks for hardirq and for softirq processing
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*/
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void irq_ctx_init(int cpu)
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{
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union irq_ctx *irqctx;
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if (hardirq_ctx[cpu])
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return;
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irqctx = (union irq_ctx*) &hardirq_stack[cpu*THREAD_SIZE];
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irqctx->tinfo.task = NULL;
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irqctx->tinfo.exec_domain = NULL;
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irqctx->tinfo.cpu = cpu;
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irqctx->tinfo.preempt_count = HARDIRQ_OFFSET;
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irqctx->tinfo.addr_limit = MAKE_MM_SEG(0);
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hardirq_ctx[cpu] = irqctx;
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irqctx = (union irq_ctx*) &softirq_stack[cpu*THREAD_SIZE];
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irqctx->tinfo.task = NULL;
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irqctx->tinfo.exec_domain = NULL;
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irqctx->tinfo.cpu = cpu;
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irqctx->tinfo.preempt_count = 0;
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irqctx->tinfo.addr_limit = MAKE_MM_SEG(0);
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softirq_ctx[cpu] = irqctx;
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printk("CPU %u irqstacks, hard=%p soft=%p\n",
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cpu,hardirq_ctx[cpu],softirq_ctx[cpu]);
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}
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void irq_ctx_exit(int cpu)
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{
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hardirq_ctx[cpu] = NULL;
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}
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extern asmlinkage void __do_softirq(void);
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asmlinkage void do_softirq(void)
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{
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unsigned long flags;
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struct thread_info *curctx;
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union irq_ctx *irqctx;
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u32 *isp;
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if (in_interrupt())
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return;
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local_irq_save(flags);
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if (local_softirq_pending()) {
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curctx = current_thread_info();
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irqctx = softirq_ctx[smp_processor_id()];
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irqctx->tinfo.task = curctx->task;
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irqctx->tinfo.previous_esp = current_stack_pointer;
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/* build the stack frame on the softirq stack */
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isp = (u32*) ((char*)irqctx + sizeof(*irqctx));
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asm volatile(
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" xchgl %%ebx,%%esp \n"
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" call __do_softirq \n"
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" movl %%ebx,%%esp \n"
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: "=b"(isp)
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: "0"(isp)
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: "memory", "cc", "edx", "ecx", "eax"
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);
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/*
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* Shouldnt happen, we returned above if in_interrupt():
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*/
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WARN_ON_ONCE(softirq_count());
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}
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local_irq_restore(flags);
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}
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#endif
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/*
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* Interrupt statistics:
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*/
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atomic_t irq_err_count;
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/*
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* /proc/interrupts printing:
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*/
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int show_interrupts(struct seq_file *p, void *v)
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{
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int i = *(loff_t *) v, j;
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struct irqaction * action;
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unsigned long flags;
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if (i == 0) {
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seq_printf(p, " ");
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for_each_online_cpu(j)
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seq_printf(p, "CPU%-8d",j);
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seq_putc(p, '\n');
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}
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if (i < NR_IRQS) {
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unsigned any_count = 0;
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spin_lock_irqsave(&irq_desc[i].lock, flags);
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#ifndef CONFIG_SMP
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any_count = kstat_irqs(i);
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#else
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for_each_online_cpu(j)
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any_count |= kstat_cpu(j).irqs[i];
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#endif
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action = irq_desc[i].action;
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if (!action && !any_count)
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goto skip;
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seq_printf(p, "%3d: ",i);
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#ifndef CONFIG_SMP
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seq_printf(p, "%10u ", kstat_irqs(i));
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#else
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
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#endif
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seq_printf(p, " %8s", irq_desc[i].chip->name);
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seq_printf(p, "-%-8s", irq_desc[i].name);
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if (action) {
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seq_printf(p, " %s", action->name);
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while ((action = action->next) != NULL)
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seq_printf(p, ", %s", action->name);
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}
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seq_putc(p, '\n');
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skip:
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spin_unlock_irqrestore(&irq_desc[i].lock, flags);
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} else if (i == NR_IRQS) {
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seq_printf(p, "NMI: ");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", nmi_count(j));
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seq_printf(p, " Non-maskable interrupts\n");
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#ifdef CONFIG_X86_LOCAL_APIC
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seq_printf(p, "LOC: ");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ",
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per_cpu(irq_stat,j).apic_timer_irqs);
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seq_printf(p, " Local timer interrupts\n");
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#endif
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#ifdef CONFIG_SMP
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seq_printf(p, "RES: ");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ",
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per_cpu(irq_stat,j).irq_resched_count);
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seq_printf(p, " Rescheduling interrupts\n");
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seq_printf(p, "CAL: ");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ",
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per_cpu(irq_stat,j).irq_call_count);
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seq_printf(p, " function call interrupts\n");
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seq_printf(p, "TLB: ");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ",
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per_cpu(irq_stat,j).irq_tlb_count);
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seq_printf(p, " TLB shootdowns\n");
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#endif
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seq_printf(p, "TRM: ");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ",
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per_cpu(irq_stat,j).irq_thermal_count);
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seq_printf(p, " Thermal event interrupts\n");
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seq_printf(p, "SPU: ");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ",
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per_cpu(irq_stat,j).irq_spurious_count);
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seq_printf(p, " Spurious interrupts\n");
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seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
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#if defined(CONFIG_X86_IO_APIC)
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seq_printf(p, "MIS: %10u\n", atomic_read(&irq_mis_count));
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#endif
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}
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return 0;
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}
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#ifdef CONFIG_HOTPLUG_CPU
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#include <mach_apic.h>
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void fixup_irqs(cpumask_t map)
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{
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unsigned int irq;
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static int warned;
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for (irq = 0; irq < NR_IRQS; irq++) {
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cpumask_t mask;
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if (irq == 2)
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continue;
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cpus_and(mask, irq_desc[irq].affinity, map);
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if (any_online_cpu(mask) == NR_CPUS) {
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printk("Breaking affinity for irq %i\n", irq);
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mask = map;
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}
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if (irq_desc[irq].chip->set_affinity)
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irq_desc[irq].chip->set_affinity(irq, mask);
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else if (irq_desc[irq].action && !(warned++))
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printk("Cannot set affinity for irq %i\n", irq);
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}
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#if 0
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barrier();
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/* Ingo Molnar says: "after the IO-APIC masks have been redirected
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[note the nop - the interrupt-enable boundary on x86 is two
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instructions from sti] - to flush out pending hardirqs and
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IPIs. After this point nothing is supposed to reach this CPU." */
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__asm__ __volatile__("sti; nop; cli");
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barrier();
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#else
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/* That doesn't seem sufficient. Give it 1ms. */
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local_irq_enable();
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mdelay(1);
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local_irq_disable();
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#endif
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}
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#endif
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