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121 lines
3.7 KiB
121 lines
3.7 KiB
/*
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* arch/arm/mach-pnx4008/irq.c
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*
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* PNX4008 IRQ controller driver
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*
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* Author: Dmitry Chigirev <source@mvista.com>
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*
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* Based on reference code received from Philips:
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* Copyright (C) 2003 Philips Semiconductors
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*
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* 2005 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/device.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/setup.h>
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#include <asm/mach-types.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/system.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/map.h>
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#include <asm/arch/irq.h>
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static u8 pnx4008_irq_type[NR_IRQS] = PNX4008_IRQ_TYPES;
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static void pnx4008_mask_irq(unsigned int irq)
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{
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__raw_writel(__raw_readl(INTC_ER(irq)) & ~INTC_BIT(irq), INTC_ER(irq)); /* mask interrupt */
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}
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static void pnx4008_unmask_irq(unsigned int irq)
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{
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__raw_writel(__raw_readl(INTC_ER(irq)) | INTC_BIT(irq), INTC_ER(irq)); /* unmask interrupt */
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}
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static void pnx4008_mask_ack_irq(unsigned int irq)
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{
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__raw_writel(__raw_readl(INTC_ER(irq)) & ~INTC_BIT(irq), INTC_ER(irq)); /* mask interrupt */
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__raw_writel(INTC_BIT(irq), INTC_SR(irq)); /* clear interrupt status */
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}
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static int pnx4008_set_irq_type(unsigned int irq, unsigned int type)
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{
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switch (type) {
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case IRQT_RISING:
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__raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */
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__raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /*rising edge */
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set_irq_handler(irq, do_edge_IRQ);
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break;
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case IRQT_FALLING:
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__raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */
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__raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*falling edge */
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set_irq_handler(irq, do_edge_IRQ);
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break;
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case IRQT_LOW:
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__raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */
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__raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*low level */
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set_irq_handler(irq, do_level_IRQ);
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break;
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case IRQT_HIGH:
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__raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */
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__raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /* high level */
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set_irq_handler(irq, do_level_IRQ);
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break;
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/* IRQT_BOTHEDGE is not supported */
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default:
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printk(KERN_ERR "PNX4008 IRQ: Unsupported irq type %d\n", type);
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return -1;
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}
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return 0;
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}
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static struct irqchip pnx4008_irq_chip = {
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.ack = pnx4008_mask_ack_irq,
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.mask = pnx4008_mask_irq,
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.unmask = pnx4008_unmask_irq,
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.set_type = pnx4008_set_irq_type,
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};
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void __init pnx4008_init_irq(void)
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{
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unsigned int i;
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/* configure and enable IRQ 0,1,30,31 (cascade interrupts) mask all others */
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pnx4008_set_irq_type(SUB1_IRQ_N, pnx4008_irq_type[SUB1_IRQ_N]);
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pnx4008_set_irq_type(SUB2_IRQ_N, pnx4008_irq_type[SUB2_IRQ_N]);
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pnx4008_set_irq_type(SUB1_FIQ_N, pnx4008_irq_type[SUB1_FIQ_N]);
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pnx4008_set_irq_type(SUB2_FIQ_N, pnx4008_irq_type[SUB2_FIQ_N]);
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__raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) |
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(1 << SUB2_IRQ_N) | (1 << SUB1_IRQ_N),
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INTC_ER(MAIN_BASE_INT));
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__raw_writel(0, INTC_ER(SIC1_BASE_INT));
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__raw_writel(0, INTC_ER(SIC2_BASE_INT));
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/* configure all other IRQ's */
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for (i = 0; i < NR_IRQS; i++) {
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if (i == SUB2_FIQ_N || i == SUB1_FIQ_N ||
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i == SUB2_IRQ_N || i == SUB1_IRQ_N)
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continue;
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set_irq_flags(i, IRQF_VALID);
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set_irq_chip(i, &pnx4008_irq_chip);
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pnx4008_set_irq_type(i, pnx4008_irq_type[i]);
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}
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}
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