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219 lines
5.2 KiB
219 lines
5.2 KiB
/*
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* linux/arch/arm/mach-pxa/cm-x270-pci.c
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*
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* PCI bios-type initialisation for PCI machines
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*
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* Bits taken from various places.
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*
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* Copyright (C) 2007 Compulab, Ltd.
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* Mike Rapoport <mike@compulab.co.il>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/irq.h>
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#include <asm/mach/pci.h>
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#include <asm/arch/cm-x270.h>
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#include <asm/arch/pxa-regs.h>
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#include <asm/arch/pxa2xx-gpio.h>
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#include <asm/mach-types.h>
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#include <asm/hardware/it8152.h>
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unsigned long it8152_base_address = CMX270_IT8152_VIRT;
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/*
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* Only first 64MB of memory can be accessed via PCI.
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* We use GFP_DMA to allocate safe buffers to do map/unmap.
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* This is really ugly and we need a better way of specifying
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* DMA-capable regions of memory.
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*/
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void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size,
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unsigned long *zhole_size)
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{
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unsigned int sz = SZ_64M >> PAGE_SHIFT;
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if (machine_is_armcore()) {
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pr_info("Adjusting zones for CM-x270\n");
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/*
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* Only adjust if > 64M on current system
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*/
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if (node || (zone_size[0] <= sz))
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return;
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zone_size[1] = zone_size[0] - sz;
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zone_size[0] = sz;
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zhole_size[1] = zhole_size[0];
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zhole_size[0] = 0;
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}
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}
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static void cmx270_it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
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{
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/* clear our parent irq */
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GEDR(GPIO_IT8152_IRQ) = GPIO_bit(GPIO_IT8152_IRQ);
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it8152_irq_demux(irq, desc);
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}
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void __cmx270_pci_init_irq(void)
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{
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it8152_init_irq();
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pxa_gpio_mode(IRQ_TO_GPIO(GPIO_IT8152_IRQ));
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set_irq_type(IRQ_GPIO(GPIO_IT8152_IRQ), IRQT_RISING);
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set_irq_chained_handler(IRQ_GPIO(GPIO_IT8152_IRQ),
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cmx270_it8152_irq_demux);
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}
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#ifdef CONFIG_PM
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static unsigned long sleep_save_ite[10];
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void __cmx270_pci_suspend(void)
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{
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/* save ITE state */
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sleep_save_ite[0] = __raw_readl(IT8152_INTC_PDCNIMR);
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sleep_save_ite[1] = __raw_readl(IT8152_INTC_LPCNIMR);
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sleep_save_ite[2] = __raw_readl(IT8152_INTC_LPNIAR);
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/* Clear ITE IRQ's */
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__raw_writel((0), IT8152_INTC_PDCNIRR);
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__raw_writel((0), IT8152_INTC_LPCNIRR);
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}
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void __cmx270_pci_resume(void)
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{
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/* restore IT8152 state */
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__raw_writel((sleep_save_ite[0]), IT8152_INTC_PDCNIMR);
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__raw_writel((sleep_save_ite[1]), IT8152_INTC_LPCNIMR);
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__raw_writel((sleep_save_ite[2]), IT8152_INTC_LPNIAR);
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}
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#else
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void cmx270_pci_suspend(void) {}
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void cmx270_pci_resume(void) {}
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#endif
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/* PCI IRQ mapping*/
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static int __init cmx270_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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int irq;
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dev_dbg(&dev->dev, "%s: slot=%x, pin=%x\n", __func__, slot, pin);
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irq = it8152_pci_map_irq(dev, slot, pin);
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if (irq)
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return irq;
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/*
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Here comes the ugly part. The routing is baseboard specific,
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but defining a platform for each possible base of CM-x270 is
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unrealistic. Here we keep mapping for ATXBase and SB-x270.
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*/
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/* ATXBASE PCI slot */
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if (slot == 7)
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return IT8152_PCI_INTA;
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/* ATXBase/SB-x270 CardBus */
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if (slot == 8 || slot == 0)
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return IT8152_PCI_INTB;
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/* ATXBase Ethernet */
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if (slot == 9)
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return IT8152_PCI_INTA;
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/* SB-x270 Ethernet */
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if (slot == 16)
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return IT8152_PCI_INTA;
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/* PC104+ interrupt routing */
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if ((slot == 17) || (slot == 19))
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return IT8152_PCI_INTA;
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if ((slot == 18) || (slot == 20))
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return IT8152_PCI_INTB;
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return(0);
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}
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static void cmx270_pci_preinit(void)
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{
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pr_info("Initializing CM-X270 PCI subsystem\n");
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__raw_writel(0x800, IT8152_PCI_CFG_ADDR);
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if (__raw_readl(IT8152_PCI_CFG_DATA) == 0x81521283) {
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pr_info("PCI Bridge found.\n");
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/* set PCI I/O base at 0 */
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writel(0x848, IT8152_PCI_CFG_ADDR);
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writel(0, IT8152_PCI_CFG_DATA);
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/* set PCI memory base at 0 */
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writel(0x840, IT8152_PCI_CFG_ADDR);
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writel(0, IT8152_PCI_CFG_DATA);
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writel(0x20, IT8152_GPIO_GPDR);
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/* CardBus Controller on ATXbase baseboard */
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writel(0x4000, IT8152_PCI_CFG_ADDR);
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if (readl(IT8152_PCI_CFG_DATA) == 0xAC51104C) {
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pr_info("CardBus Bridge found.\n");
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/* Configure socket 0 */
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writel(0x408C, IT8152_PCI_CFG_ADDR);
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writel(0x1022, IT8152_PCI_CFG_DATA);
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writel(0x4080, IT8152_PCI_CFG_ADDR);
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writel(0x3844d060, IT8152_PCI_CFG_DATA);
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writel(0x4090, IT8152_PCI_CFG_ADDR);
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writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) |
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0x60440000),
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IT8152_PCI_CFG_DATA);
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writel(0x4018, IT8152_PCI_CFG_ADDR);
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writel(0xb0000000, IT8152_PCI_CFG_DATA);
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/* Configure socket 1 */
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writel(0x418C, IT8152_PCI_CFG_ADDR);
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writel(0x1022, IT8152_PCI_CFG_DATA);
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writel(0x4180, IT8152_PCI_CFG_ADDR);
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writel(0x3844d060, IT8152_PCI_CFG_DATA);
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writel(0x4190, IT8152_PCI_CFG_ADDR);
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writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) |
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0x60440000),
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IT8152_PCI_CFG_DATA);
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writel(0x4118, IT8152_PCI_CFG_ADDR);
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writel(0xb0000000, IT8152_PCI_CFG_DATA);
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}
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}
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}
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static struct hw_pci cmx270_pci __initdata = {
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.swizzle = pci_std_swizzle,
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.map_irq = cmx270_pci_map_irq,
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.nr_controllers = 1,
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.setup = it8152_pci_setup,
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.scan = it8152_pci_scan_bus,
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.preinit = cmx270_pci_preinit,
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};
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static int __init cmx270_init_pci(void)
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{
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if (machine_is_armcore())
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pci_common_init(&cmx270_pci);
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return 0;
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}
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subsys_initcall(cmx270_init_pci);
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