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464 lines
12 KiB
464 lines
12 KiB
/*
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* SuperH Ethernet device driver
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*
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* Copyright (C) 2006-2008 Nobuhiro Iwamatsu
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* Copyright (C) 2008 Renesas Solutions Corp.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* The full GNU General Public License is included in this distribution in
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* the file called "COPYING".
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*/
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#ifndef __SH_ETH_H__
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#define __SH_ETH_H__
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/workqueue.h>
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#include <linux/netdevice.h>
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#include <linux/phy.h>
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#define CARDNAME "sh-eth"
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#define TX_TIMEOUT (5*HZ)
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#define TX_RING_SIZE 128 /* Tx ring size */
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#define RX_RING_SIZE 128 /* Rx ring size */
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#define RX_OFFSET 2 /* skb offset */
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#define ETHERSMALL 60
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#define PKT_BUF_SZ 1538
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/* Chip Base Address */
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#define SH_TSU_ADDR 0xA7000804
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/* Chip Registers */
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/* E-DMAC */
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#define EDMR 0x0000
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#define EDTRR 0x0004
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#define EDRRR 0x0008
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#define TDLAR 0x000C
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#define RDLAR 0x0010
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#define EESR 0x0014
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#define EESIPR 0x0018
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#define TRSCER 0x001C
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#define RMFCR 0x0020
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#define TFTR 0x0024
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#define FDR 0x0028
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#define RMCR 0x002C
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#define EDOCR 0x0030
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#define FCFTR 0x0034
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#define RPADIR 0x0038
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#define TRIMD 0x003C
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#define RBWAR 0x0040
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#define RDFAR 0x0044
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#define TBRAR 0x004C
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#define TDFAR 0x0050
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/* Ether Register */
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#define ECMR 0x0160
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#define ECSR 0x0164
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#define ECSIPR 0x0168
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#define PIR 0x016C
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#define MAHR 0x0170
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#define MALR 0x0174
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#define RFLR 0x0178
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#define PSR 0x017C
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#define TROCR 0x0180
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#define CDCR 0x0184
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#define LCCR 0x0188
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#define CNDCR 0x018C
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#define CEFCR 0x0194
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#define FRECR 0x0198
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#define TSFRCR 0x019C
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#define TLFRCR 0x01A0
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#define RFCR 0x01A4
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#define MAFCR 0x01A8
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#define IPGR 0x01B4
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#if defined(CONFIG_CPU_SUBTYPE_SH7710)
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#define APR 0x01B8
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#define MPR 0x01BC
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#define TPAUSER 0x1C4
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#define BCFR 0x1CC
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#endif /* CONFIG_CPU_SH7710 */
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#define ARSTR 0x0800
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/* TSU */
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#define TSU_CTRST 0x004
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#define TSU_FWEN0 0x010
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#define TSU_FWEN1 0x014
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#define TSU_FCM 0x018
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#define TSU_BSYSL0 0x020
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#define TSU_BSYSL1 0x024
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#define TSU_PRISL0 0x028
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#define TSU_PRISL1 0x02C
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#define TSU_FWSL0 0x030
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#define TSU_FWSL1 0x034
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#define TSU_FWSLC 0x038
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#define TSU_QTAGM0 0x040
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#define TSU_QTAGM1 0x044
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#define TSU_ADQT0 0x048
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#define TSU_ADQT1 0x04C
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#define TSU_FWSR 0x050
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#define TSU_FWINMK 0x054
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#define TSU_ADSBSY 0x060
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#define TSU_TEN 0x064
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#define TSU_POST1 0x070
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#define TSU_POST2 0x074
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#define TSU_POST3 0x078
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#define TSU_POST4 0x07C
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#define TXNLCR0 0x080
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#define TXALCR0 0x084
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#define RXNLCR0 0x088
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#define RXALCR0 0x08C
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#define FWNLCR0 0x090
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#define FWALCR0 0x094
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#define TXNLCR1 0x0A0
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#define TXALCR1 0x0A4
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#define RXNLCR1 0x0A8
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#define RXALCR1 0x0AC
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#define FWNLCR1 0x0B0
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#define FWALCR1 0x0B4
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#define TSU_ADRH0 0x0100
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#define TSU_ADRL0 0x0104
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#define TSU_ADRL31 0x01FC
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/* Register's bits */
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/* EDMR */
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enum DMAC_M_BIT {
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EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, EDMR_SRST = 0x01,
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};
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/* EDTRR */
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enum DMAC_T_BIT {
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EDTRR_TRNS = 0x01,
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};
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/* EDRRR*/
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enum EDRRR_R_BIT {
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EDRRR_R = 0x01,
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};
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/* TPAUSER */
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enum TPAUSER_BIT {
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TPAUSER_TPAUSE = 0x0000ffff,
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TPAUSER_UNLIMITED = 0,
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};
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/* BCFR */
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enum BCFR_BIT {
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BCFR_RPAUSE = 0x0000ffff,
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BCFR_UNLIMITED = 0,
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};
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/* PIR */
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enum PIR_BIT {
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PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
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};
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/* PSR */
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enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
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/* EESR */
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enum EESR_BIT {
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EESR_TWB = 0x40000000, EESR_TABT = 0x04000000,
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EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
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EESR_ADE = 0x00800000, EESR_ECI = 0x00400000,
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EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
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EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
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EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
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EESR_TINT4 = 0x00000800, EESR_TINT3 = 0x00000400,
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EESR_TINT2 = 0x00000200, EESR_TINT1 = 0x00000100,
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EESR_RINT8 = 0x00000080, EESR_RINT5 = 0x00000010,
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EESR_RINT4 = 0x00000008, EESR_RINT3 = 0x00000004,
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EESR_RINT2 = 0x00000002, EESR_RINT1 = 0x00000001,
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};
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#define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
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| EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
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/* EESIPR */
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enum DMAC_IM_BIT {
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DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
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DMAC_M_RABT = 0x02000000,
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DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
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DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
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DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
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DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
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DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
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DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
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DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
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DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
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DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
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DMAC_M_RINT1 = 0x00000001,
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};
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/* Receive descriptor bit */
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enum RD_STS_BIT {
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RD_RACT = 0x80000000, RC_RDEL = 0x40000000,
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RC_RFP1 = 0x20000000, RC_RFP0 = 0x10000000,
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RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
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RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
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RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
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RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
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RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
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RD_RFS1 = 0x00000001,
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};
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#define RDF1ST RC_RFP1
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#define RDFEND RC_RFP0
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#define RD_RFP (RC_RFP1|RC_RFP0)
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/* FCFTR */
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enum FCFTR_BIT {
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FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
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FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
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FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
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};
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#define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
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#define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
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/* Transfer descriptor bit */
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enum TD_STS_BIT {
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TD_TACT = 0x80000000, TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
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TD_TFP0 = 0x10000000,
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};
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#define TDF1ST TD_TFP1
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#define TDFEND TD_TFP0
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#define TD_TFP (TD_TFP1|TD_TFP0)
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/* RMCR */
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enum RECV_RST_BIT { RMCR_RST = 0x01, };
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/* ECMR */
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enum FELIC_MODE_BIT {
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ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
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ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
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ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
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ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
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ECMR_PRM = 0x00000001,
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};
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/* ECSR */
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enum ECSR_STATUS_BIT {
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ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, ECSR_LCHNG = 0x04,
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ECSR_MPD = 0x02, ECSR_ICD = 0x01,
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};
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/* ECSIPR */
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enum ECSIPR_STATUS_MASK_BIT {
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ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10, ECSIPR_LCHNGIP = 0x04,
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ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
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};
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/* APR */
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enum APR_BIT {
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APR_AP = 0x00000001,
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};
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/* MPR */
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enum MPR_BIT {
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MPR_MP = 0x00000001,
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};
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/* TRSCER */
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enum DESC_I_BIT {
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DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
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DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
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DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
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DESC_I_RINT1 = 0x0001,
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};
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/* RPADIR */
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enum RPADIR_BIT {
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RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
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RPADIR_PADR = 0x0003f,
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};
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/* FDR */
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enum FIFO_SIZE_BIT {
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FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
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};
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enum phy_offsets {
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PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3,
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PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6,
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PHY_16 = 16,
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};
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/* PHY_CTRL */
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enum PHY_CTRL_BIT {
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PHY_C_RESET = 0x8000, PHY_C_LOOPBK = 0x4000, PHY_C_SPEEDSL = 0x2000,
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PHY_C_ANEGEN = 0x1000, PHY_C_PWRDN = 0x0800, PHY_C_ISO = 0x0400,
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PHY_C_RANEG = 0x0200, PHY_C_DUPLEX = 0x0100, PHY_C_COLT = 0x0080,
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};
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#define DM9161_PHY_C_ANEGEN 0 /* auto nego special */
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/* PHY_STAT */
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enum PHY_STAT_BIT {
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PHY_S_100T4 = 0x8000, PHY_S_100X_F = 0x4000, PHY_S_100X_H = 0x2000,
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PHY_S_10T_F = 0x1000, PHY_S_10T_H = 0x0800, PHY_S_ANEGC = 0x0020,
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PHY_S_RFAULT = 0x0010, PHY_S_ANEGA = 0x0008, PHY_S_LINK = 0x0004,
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PHY_S_JAB = 0x0002, PHY_S_EXTD = 0x0001,
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};
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/* PHY_ANA */
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enum PHY_ANA_BIT {
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PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000,
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PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100,
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PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020,
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PHY_A_SEL = 0x001f,
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};
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/* PHY_ANL */
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enum PHY_ANL_BIT {
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PHY_L_NP = 0x8000, PHY_L_ACK = 0x4000, PHY_L_RF = 0x2000,
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PHY_L_FCS = 0x0400, PHY_L_T4 = 0x0200, PHY_L_FDX = 0x0100,
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PHY_L_HDX = 0x0080, PHY_L_10FDX = 0x0040, PHY_L_10HDX = 0x0020,
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PHY_L_SEL = 0x001f,
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};
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/* PHY_ANE */
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enum PHY_ANE_BIT {
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PHY_E_PDF = 0x0010, PHY_E_LPNPA = 0x0008, PHY_E_NPA = 0x0004,
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PHY_E_PRX = 0x0002, PHY_E_LPANEGA = 0x0001,
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};
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/* DM9161 */
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enum PHY_16_BIT {
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PHY_16_BP4B45 = 0x8000, PHY_16_BPSCR = 0x4000, PHY_16_BPALIGN = 0x2000,
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PHY_16_BP_ADPOK = 0x1000, PHY_16_Repeatmode = 0x0800,
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PHY_16_TXselect = 0x0400,
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PHY_16_Rsvd = 0x0200, PHY_16_RMIIEnable = 0x0100,
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PHY_16_Force100LNK = 0x0080,
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PHY_16_APDLED_CTL = 0x0040, PHY_16_COLLED_CTL = 0x0020,
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PHY_16_RPDCTR_EN = 0x0010,
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PHY_16_ResetStMch = 0x0008, PHY_16_PreamSupr = 0x0004,
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PHY_16_Sleepmode = 0x0002,
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PHY_16_RemoteLoopOut = 0x0001,
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};
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#define POST_RX 0x08
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#define POST_FW 0x04
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#define POST0_RX (POST_RX)
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#define POST0_FW (POST_FW)
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#define POST1_RX (POST_RX >> 2)
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#define POST1_FW (POST_FW >> 2)
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#define POST_ALL (POST0_RX | POST0_FW | POST1_RX | POST1_FW)
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/* ARSTR */
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enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, };
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/* TSU_FWEN0 */
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enum TSU_FWEN0_BIT {
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TSU_FWEN0_0 = 0x00000001,
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};
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/* TSU_ADSBSY */
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enum TSU_ADSBSY_BIT {
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TSU_ADSBSY_0 = 0x00000001,
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};
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/* TSU_TEN */
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enum TSU_TEN_BIT {
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TSU_TEN_0 = 0x80000000,
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};
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/* TSU_FWSL0 */
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enum TSU_FWSL0_BIT {
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TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
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TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
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TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
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};
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/* TSU_FWSLC */
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enum TSU_FWSLC_BIT {
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TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
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TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
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TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
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TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
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TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
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};
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/*
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* The sh ether Tx buffer descriptors.
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* This structure should be 20 bytes.
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*/
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struct sh_eth_txdesc {
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u32 status; /* TD0 */
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#if defined(CONFIG_CPU_LITTLE_ENDIAN)
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u16 pad0; /* TD1 */
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u16 buffer_length; /* TD1 */
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#else
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u16 buffer_length; /* TD1 */
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u16 pad0; /* TD1 */
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#endif
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u32 addr; /* TD2 */
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u32 pad1; /* padding data */
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};
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/*
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* The sh ether Rx buffer descriptors.
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* This structure should be 20 bytes.
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*/
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struct sh_eth_rxdesc {
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u32 status; /* RD0 */
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#if defined(CONFIG_CPU_LITTLE_ENDIAN)
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u16 frame_length; /* RD1 */
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u16 buffer_length; /* RD1 */
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#else
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u16 buffer_length; /* RD1 */
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u16 frame_length; /* RD1 */
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#endif
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u32 addr; /* RD2 */
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u32 pad0; /* padding data */
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};
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struct sh_eth_private {
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dma_addr_t rx_desc_dma;
|
|
dma_addr_t tx_desc_dma;
|
|
struct sh_eth_rxdesc *rx_ring;
|
|
struct sh_eth_txdesc *tx_ring;
|
|
struct sk_buff **rx_skbuff;
|
|
struct sk_buff **tx_skbuff;
|
|
struct net_device_stats stats;
|
|
struct timer_list timer;
|
|
spinlock_t lock;
|
|
u32 cur_rx, dirty_rx; /* Producer/consumer ring indices */
|
|
u32 cur_tx, dirty_tx;
|
|
u32 rx_buf_sz; /* Based on MTU+slack. */
|
|
/* MII transceiver section. */
|
|
u32 phy_id; /* PHY ID */
|
|
struct mii_bus *mii_bus; /* MDIO bus control */
|
|
struct phy_device *phydev; /* PHY device control */
|
|
enum phy_state link;
|
|
int msg_enable;
|
|
int speed;
|
|
int duplex;
|
|
u32 rx_int_var, tx_int_var; /* interrupt control variables */
|
|
char post_rx; /* POST receive */
|
|
char post_fw; /* POST forward */
|
|
struct net_device_stats tsu_stats; /* TSU forward status */
|
|
};
|
|
|
|
static void swaps(char *src, int len)
|
|
{
|
|
#ifdef __LITTLE_ENDIAN__
|
|
u32 *p = (u32 *)src;
|
|
u32 *maxp;
|
|
maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
|
|
|
|
for (; p < maxp; p++)
|
|
*p = swab32(*p);
|
|
#endif
|
|
}
|
|
|
|
#endif
|
|
|