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203 lines
6.9 KiB
203 lines
6.9 KiB
/*
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* arch/ppc/platform/85xx/sbc85xx.c
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*
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* WindRiver PowerQUICC III SBC85xx board common routines
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*
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* Copyright 2002, 2003 Motorola Inc.
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* Copyright 2004 Red Hat, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/major.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/seq_file.h>
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#include <linux/serial.h>
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#include <linux/module.h>
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#include <asm/system.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/atomic.h>
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#include <asm/time.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/prom.h>
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#include <asm/open_pic.h>
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#include <asm/bootinfo.h>
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#include <asm/pci-bridge.h>
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#include <asm/mpc85xx.h>
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#include <asm/irq.h>
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#include <asm/immap_85xx.h>
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#include <asm/ppc_sys.h>
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#include <mm/mmu_decl.h>
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#include <platforms/85xx/sbc85xx.h>
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unsigned char __res[sizeof (bd_t)];
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#ifndef CONFIG_PCI
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unsigned long isa_io_base = 0;
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unsigned long isa_mem_base = 0;
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unsigned long pci_dram_offset = 0;
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#endif
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extern unsigned long total_memory; /* in mm/init */
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/* Internal interrupts are all Level Sensitive, and Positive Polarity */
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static u_char sbc8560_openpic_initsenses[] __initdata = {
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: L2 Cache */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: ECM */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCI/PCI-X */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: RIO Inbound Port Write Error */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: RIO Doorbell Inbound */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: RIO Outbound Message */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: RIO Inbound Message */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 0 Transmit */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 0 Receive */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: Unused */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: Unused */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: Unused */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 0 Receive/Transmit Error */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 1 Transmit */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 1 Receive */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: Unused */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: Unused */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: Unused */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 1 Receive/Transmit Error */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Fast Ethernet */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: CPM */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
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0x0, /* External 0: */
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0x0, /* External 1: */
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#if defined(CONFIG_PCI)
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI slot 0 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI slot 1 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 4: PCI slot 2 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PCI slot 3 */
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#else
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0x0, /* External 2: */
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0x0, /* External 3: */
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0x0, /* External 4: */
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0x0, /* External 5: */
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#endif
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 6: PHY */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 7: PHY */
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0x0, /* External 8: */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* External 9: PHY */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* External 10: PHY */
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0x0, /* External 11: */
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};
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/* ************************************************************************ */
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int
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sbc8560_show_cpuinfo(struct seq_file *m)
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{
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uint pvid, svid, phid1;
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uint memsize = total_memory;
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bd_t *binfo = (bd_t *) __res;
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unsigned int freq;
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/* get the core frequency */
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freq = binfo->bi_intfreq;
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pvid = mfspr(SPRN_PVR);
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svid = mfspr(SPRN_SVR);
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seq_printf(m, "Vendor\t\t: Wind River\n");
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seq_printf(m, "Machine\t\t: SBC%s\n", cur_ppc_sys_spec->ppc_sys_name);
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seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
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seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
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seq_printf(m, "SVR\t\t: 0x%x\n", svid);
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/* Display cpu Pll setting */
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phid1 = mfspr(SPRN_HID1);
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seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
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/* Display the amount of memory */
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seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
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return 0;
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}
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void __init
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sbc8560_init_IRQ(void)
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{
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bd_t *binfo = (bd_t *) __res;
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/* Determine the Physical Address of the OpenPIC regs */
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phys_addr_t OpenPIC_PAddr =
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binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
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OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
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OpenPIC_InitSenses = sbc8560_openpic_initsenses;
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OpenPIC_NumInitSenses = sizeof (sbc8560_openpic_initsenses);
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/* Skip reserved space and internal sources */
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openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
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/* Map PIC IRQs 0-11 */
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openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000);
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/* we let openpic interrupts starting from an offset, to
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* leave space for cascading interrupts underneath.
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*/
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openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
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return;
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}
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/*
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* interrupt routing
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*/
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#ifdef CONFIG_PCI
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int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel,
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unsigned char pin)
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{
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static char pci_irq_table[][4] =
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/*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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{
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{PIRQA, PIRQB, PIRQC, PIRQD},
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{PIRQD, PIRQA, PIRQB, PIRQC},
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{PIRQC, PIRQD, PIRQA, PIRQB},
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{PIRQB, PIRQC, PIRQD, PIRQA},
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};
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const long min_idsel = 12, max_idsel = 15, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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}
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int mpc85xx_exclude_device(u_char bus, u_char devfn)
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{
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if (bus == 0 && PCI_SLOT(devfn) == 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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else
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return PCIBIOS_SUCCESSFUL;
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}
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#endif /* CONFIG_PCI */
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