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Ke Wei 1219715de7 [ARM] Orion: add a separate BRIDGE_INT_TIMER1_CLR define ... Some Feroceon-based SoCs have an MBUS bridge interrupt controller that requires writing a one instead of a zero to clear edge interrupt sources such as timer expiry. This patch adds a new BRIDGE_INT_TIMER1_CLR define, which platform code can set to either ~BRIDGE_INT_TIMER1 (write-zero-to-clear) or BRIDGE_INT_TIMER1 (write-one-to-clear) depending on the platform. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>		17 years ago
..
debug-macro.S	…
dma.h	…
entry-macro.S	…
gpio.h	Orion: orion -> orion5x rename	17 years ago
hardware.h	Orion: orion -> orion5x rename	17 years ago
io.h	[ARM] Orion: nuke orion5x_{read,write}	17 years ago
irqs.h	…
memory.h	…
orion5x.h	[ARM] Orion: add a separate BRIDGE_INT_TIMER1_CLR define	17 years ago
system.h	Orion: orion -> orion5x rename	17 years ago
timex.h	…
uncompress.h	[ARM] Orion: use linux/serial_reg.h for Orion uncompress.h	17 years ago
vmalloc.h	…