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514 lines
14 KiB
514 lines
14 KiB
/*
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drivers/net/tulip/tulip.h
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Copyright 2000,2001 The Linux Kernel Team
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Written/copyright 1994-2001 by Donald Becker.
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This software may be used and distributed according to the terms
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of the GNU General Public License, incorporated herein by reference.
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Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
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for more information on this driver, or visit the project
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Web page at http://sourceforge.net/projects/tulip/
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*/
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#ifndef __NET_TULIP_H__
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#define __NET_TULIP_H__
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/spinlock.h>
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#include <linux/netdevice.h>
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#include <linux/timer.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/unaligned.h>
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/* undefine, or define to various debugging levels (>4 == obscene levels) */
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#define TULIP_DEBUG 1
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#ifdef CONFIG_TULIP_MMIO
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#define TULIP_BAR 1 /* CBMA */
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#else
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#define TULIP_BAR 0 /* CBIO */
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#endif
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struct tulip_chip_table {
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char *chip_name;
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int io_size;
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int valid_intrs; /* CSR7 interrupt enable settings */
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int flags;
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void (*media_timer) (unsigned long);
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work_func_t media_task;
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};
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enum tbl_flag {
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HAS_MII = 0x0001,
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HAS_MEDIA_TABLE = 0x0002,
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CSR12_IN_SROM = 0x0004,
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ALWAYS_CHECK_MII = 0x0008,
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HAS_ACPI = 0x0010,
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MC_HASH_ONLY = 0x0020, /* Hash-only multicast filter. */
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HAS_PNICNWAY = 0x0080,
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HAS_NWAY = 0x0040, /* Uses internal NWay xcvr. */
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HAS_INTR_MITIGATION = 0x0100,
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IS_ASIX = 0x0200,
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HAS_8023X = 0x0400,
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COMET_MAC_ADDR = 0x0800,
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HAS_PCI_MWI = 0x1000,
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HAS_PHY_IRQ = 0x2000,
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HAS_SWAPPED_SEEPROM = 0x4000,
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NEEDS_FAKE_MEDIA_TABLE = 0x8000,
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};
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/* chip types. careful! order is VERY IMPORTANT here, as these
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* are used throughout the driver as indices into arrays */
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/* Note 21142 == 21143. */
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enum chips {
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DC21040 = 0,
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DC21041 = 1,
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DC21140 = 2,
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DC21142 = 3, DC21143 = 3,
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LC82C168,
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MX98713,
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MX98715,
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MX98725,
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AX88140,
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PNIC2,
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COMET,
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COMPEX9881,
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I21145,
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DM910X,
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CONEXANT,
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};
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enum MediaIs {
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MediaIsFD = 1,
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MediaAlwaysFD = 2,
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MediaIsMII = 4,
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MediaIsFx = 8,
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MediaIs100 = 16
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};
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/* Offsets to the Command and Status Registers, "CSRs". All accesses
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must be longword instructions and quadword aligned. */
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enum tulip_offsets {
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CSR0 = 0,
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CSR1 = 0x08,
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CSR2 = 0x10,
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CSR3 = 0x18,
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CSR4 = 0x20,
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CSR5 = 0x28,
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CSR6 = 0x30,
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CSR7 = 0x38,
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CSR8 = 0x40,
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CSR9 = 0x48,
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CSR10 = 0x50,
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CSR11 = 0x58,
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CSR12 = 0x60,
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CSR13 = 0x68,
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CSR14 = 0x70,
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CSR15 = 0x78,
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};
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/* register offset and bits for CFDD PCI config reg */
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enum pci_cfg_driver_reg {
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CFDD = 0x40,
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CFDD_Sleep = (1 << 31),
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CFDD_Snooze = (1 << 30),
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};
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#define RxPollInt (RxIntr|RxNoBuf|RxDied|RxJabber)
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/* The bits in the CSR5 status registers, mostly interrupt sources. */
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enum status_bits {
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TimerInt = 0x800,
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SystemError = 0x2000,
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TPLnkFail = 0x1000,
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TPLnkPass = 0x10,
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NormalIntr = 0x10000,
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AbnormalIntr = 0x8000,
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RxJabber = 0x200,
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RxDied = 0x100,
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RxNoBuf = 0x80,
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RxIntr = 0x40,
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TxFIFOUnderflow = 0x20,
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RxErrIntr = 0x10,
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TxJabber = 0x08,
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TxNoBuf = 0x04,
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TxDied = 0x02,
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TxIntr = 0x01,
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};
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/* bit mask for CSR5 TX/RX process state */
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#define CSR5_TS 0x00700000
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#define CSR5_RS 0x000e0000
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enum tulip_mode_bits {
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TxThreshold = (1 << 22),
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FullDuplex = (1 << 9),
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TxOn = 0x2000,
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AcceptBroadcast = 0x0100,
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AcceptAllMulticast = 0x0080,
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AcceptAllPhys = 0x0040,
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AcceptRunt = 0x0008,
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RxOn = 0x0002,
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RxTx = (TxOn | RxOn),
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};
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enum tulip_busconfig_bits {
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MWI = (1 << 24),
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MRL = (1 << 23),
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MRM = (1 << 21),
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CALShift = 14,
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BurstLenShift = 8,
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};
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/* The Tulip Rx and Tx buffer descriptors. */
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struct tulip_rx_desc {
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__le32 status;
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__le32 length;
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__le32 buffer1;
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__le32 buffer2;
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};
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struct tulip_tx_desc {
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__le32 status;
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__le32 length;
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__le32 buffer1;
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__le32 buffer2; /* We use only buffer 1. */
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};
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enum desc_status_bits {
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DescOwned = 0x80000000,
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DescWholePkt = 0x60000000,
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DescEndPkt = 0x40000000,
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DescStartPkt = 0x20000000,
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DescEndRing = 0x02000000,
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DescUseLink = 0x01000000,
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RxDescFatalErr = 0x008000,
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RxWholePkt = 0x00000300,
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};
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enum t21143_csr6_bits {
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csr6_sc = (1<<31),
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csr6_ra = (1<<30),
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csr6_ign_dest_msb = (1<<26),
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csr6_mbo = (1<<25),
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csr6_scr = (1<<24), /* scramble mode flag: can't be set */
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csr6_pcs = (1<<23), /* Enables PCS functions (symbol mode requires csr6_ps be set) default is set */
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csr6_ttm = (1<<22), /* Transmit Threshold Mode, set for 10baseT, 0 for 100BaseTX */
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csr6_sf = (1<<21), /* Store and forward. If set ignores TR bits */
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csr6_hbd = (1<<19), /* Heart beat disable. Disables SQE function in 10baseT */
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csr6_ps = (1<<18), /* Port Select. 0 (defualt) = 10baseT, 1 = 100baseTX: can't be set */
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csr6_ca = (1<<17), /* Collision Offset Enable. If set uses special algorithm in low collision situations */
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csr6_trh = (1<<15), /* Transmit Threshold high bit */
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csr6_trl = (1<<14), /* Transmit Threshold low bit */
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/***************************************************************
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* This table shows transmit threshold values based on media *
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* and these two registers (from PNIC1 & 2 docs) Note: this is *
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* all meaningless if sf is set. *
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***************************************************************/
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/***********************************
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* (trh,trl) * 100BaseTX * 10BaseT *
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***********************************
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* (0,0) * 128 * 72 *
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* (0,1) * 256 * 96 *
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* (1,0) * 512 * 128 *
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* (1,1) * 1024 * 160 *
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***********************************/
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csr6_fc = (1<<12), /* Forces a collision in next transmission (for testing in loopback mode) */
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csr6_om_int_loop = (1<<10), /* internal (FIFO) loopback flag */
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csr6_om_ext_loop = (1<<11), /* external (PMD) loopback flag */
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/* set both and you get (PHY) loopback */
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csr6_fd = (1<<9), /* Full duplex mode, disables hearbeat, no loopback */
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csr6_pm = (1<<7), /* Pass All Multicast */
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csr6_pr = (1<<6), /* Promiscuous mode */
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csr6_sb = (1<<5), /* Start(1)/Stop(0) backoff counter */
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csr6_if = (1<<4), /* Inverse Filtering, rejects only addresses in address table: can't be set */
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csr6_pb = (1<<3), /* Pass Bad Frames, (1) causes even bad frames to be passed on */
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csr6_ho = (1<<2), /* Hash-only filtering mode: can't be set */
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csr6_hp = (1<<0), /* Hash/Perfect Receive Filtering Mode: can't be set */
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csr6_mask_capture = (csr6_sc | csr6_ca),
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csr6_mask_defstate = (csr6_mask_capture | csr6_mbo),
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csr6_mask_hdcap = (csr6_mask_defstate | csr6_hbd | csr6_ps),
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csr6_mask_hdcaptt = (csr6_mask_hdcap | csr6_trh | csr6_trl),
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csr6_mask_fullcap = (csr6_mask_hdcaptt | csr6_fd),
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csr6_mask_fullpromisc = (csr6_pr | csr6_pm),
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csr6_mask_filters = (csr6_hp | csr6_ho | csr6_if),
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csr6_mask_100bt = (csr6_scr | csr6_pcs | csr6_hbd),
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};
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/* Keep the ring sizes a power of two for efficiency.
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Making the Tx ring too large decreases the effectiveness of channel
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bonding and packet priority.
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There are no ill effects from too-large receive rings. */
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#define TX_RING_SIZE 32
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#define RX_RING_SIZE 128
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#define MEDIA_MASK 31
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/* The receiver on the DC21143 rev 65 can fail to close the last
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* receive descriptor in certain circumstances (see errata) when
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* using MWI. This can only occur if the receive buffer ends on
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* a cache line boundary, so the "+ 4" below ensures it doesn't.
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*/
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#define PKT_BUF_SZ (1536 + 4) /* Size of each temporary Rx buffer. */
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#define TULIP_MIN_CACHE_LINE 8 /* in units of 32-bit words */
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#if defined(__sparc__) || defined(__hppa__)
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/* The UltraSparc PCI controllers will disconnect at every 64-byte
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* crossing anyways so it makes no sense to tell Tulip to burst
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* any more than that.
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*/
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#define TULIP_MAX_CACHE_LINE 16 /* in units of 32-bit words */
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#else
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#define TULIP_MAX_CACHE_LINE 32 /* in units of 32-bit words */
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#endif
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/* Ring-wrap flag in length field, use for last ring entry.
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0x01000000 means chain on buffer2 address,
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0x02000000 means use the ring start address in CSR2/3.
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Note: Some work-alike chips do not function correctly in chained mode.
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The ASIX chip works only in chained mode.
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Thus we indicates ring mode, but always write the 'next' field for
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chained mode as well.
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*/
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#define DESC_RING_WRAP 0x02000000
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#define EEPROM_SIZE 512 /* 2 << EEPROM_ADDRLEN */
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#define RUN_AT(x) (jiffies + (x))
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#define get_u16(ptr) get_unaligned_le16((ptr))
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struct medialeaf {
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u8 type;
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u8 media;
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unsigned char *leafdata;
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};
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struct mediatable {
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u16 defaultmedia;
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u8 leafcount;
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u8 csr12dir; /* General purpose pin directions. */
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unsigned has_mii:1;
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unsigned has_nonmii:1;
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unsigned has_reset:6;
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u32 csr15dir;
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u32 csr15val; /* 21143 NWay setting. */
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struct medialeaf mleaf[0];
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};
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struct mediainfo {
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struct mediainfo *next;
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int info_type;
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int index;
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unsigned char *info;
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};
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struct ring_info {
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struct sk_buff *skb;
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dma_addr_t mapping;
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};
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struct tulip_private {
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const char *product_name;
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struct net_device *next_module;
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struct tulip_rx_desc *rx_ring;
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struct tulip_tx_desc *tx_ring;
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dma_addr_t rx_ring_dma;
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dma_addr_t tx_ring_dma;
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/* The saved address of a sent-in-place packet/buffer, for skfree(). */
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struct ring_info tx_buffers[TX_RING_SIZE];
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/* The addresses of receive-in-place skbuffs. */
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struct ring_info rx_buffers[RX_RING_SIZE];
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u16 setup_frame[96]; /* Pseudo-Tx frame to init address table. */
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int chip_id;
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int revision;
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int flags;
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struct napi_struct napi;
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struct net_device_stats stats;
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struct timer_list timer; /* Media selection timer. */
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struct timer_list oom_timer; /* Out of memory timer. */
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u32 mc_filter[2];
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spinlock_t lock;
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spinlock_t mii_lock;
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unsigned int cur_rx, cur_tx; /* The next free ring entry */
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unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
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#ifdef CONFIG_TULIP_NAPI_HW_MITIGATION
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int mit_on;
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#endif
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unsigned int full_duplex:1; /* Full-duplex operation requested. */
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unsigned int full_duplex_lock:1;
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unsigned int fake_addr:1; /* Multiport board faked address. */
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unsigned int default_port:4; /* Last dev->if_port value. */
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unsigned int media2:4; /* Secondary monitored media port. */
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unsigned int medialock:1; /* Don't sense media type. */
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unsigned int mediasense:1; /* Media sensing in progress. */
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unsigned int nway:1, nwayset:1; /* 21143 internal NWay. */
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unsigned int timeout_recovery:1;
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unsigned int csr0; /* CSR0 setting. */
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unsigned int csr6; /* Current CSR6 control settings. */
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unsigned char eeprom[EEPROM_SIZE]; /* Serial EEPROM contents. */
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void (*link_change) (struct net_device * dev, int csr5);
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u16 sym_advertise, mii_advertise; /* NWay capabilities advertised. */
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u16 lpar; /* 21143 Link partner ability. */
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u16 advertising[4];
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signed char phys[4], mii_cnt; /* MII device addresses. */
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struct mediatable *mtable;
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int cur_index; /* Current media index. */
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int saved_if_port;
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struct pci_dev *pdev;
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int ttimer;
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int susp_rx;
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unsigned long nir;
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void __iomem *base_addr;
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int csr12_shadow;
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int pad0; /* Used for 8-byte alignment */
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struct work_struct media_work;
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struct net_device *dev;
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};
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struct eeprom_fixup {
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char *name;
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unsigned char addr0;
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unsigned char addr1;
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unsigned char addr2;
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u16 newtable[32]; /* Max length below. */
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};
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/* 21142.c */
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extern u16 t21142_csr14[];
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void t21142_media_task(struct work_struct *work);
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void t21142_start_nway(struct net_device *dev);
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void t21142_lnk_change(struct net_device *dev, int csr5);
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/* PNIC2.c */
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void pnic2_lnk_change(struct net_device *dev, int csr5);
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void pnic2_timer(unsigned long data);
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void pnic2_start_nway(struct net_device *dev);
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void pnic2_lnk_change(struct net_device *dev, int csr5);
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/* eeprom.c */
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void tulip_parse_eeprom(struct net_device *dev);
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int tulip_read_eeprom(struct net_device *dev, int location, int addr_len);
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/* interrupt.c */
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extern unsigned int tulip_max_interrupt_work;
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extern int tulip_rx_copybreak;
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irqreturn_t tulip_interrupt(int irq, void *dev_instance);
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int tulip_refill_rx(struct net_device *dev);
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#ifdef CONFIG_TULIP_NAPI
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int tulip_poll(struct napi_struct *napi, int budget);
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#endif
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/* media.c */
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int tulip_mdio_read(struct net_device *dev, int phy_id, int location);
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void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int value);
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void tulip_select_media(struct net_device *dev, int startup);
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int tulip_check_duplex(struct net_device *dev);
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void tulip_find_mii (struct net_device *dev, int board_idx);
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/* pnic.c */
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void pnic_do_nway(struct net_device *dev);
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void pnic_lnk_change(struct net_device *dev, int csr5);
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void pnic_timer(unsigned long data);
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/* timer.c */
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void tulip_media_task(struct work_struct *work);
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void mxic_timer(unsigned long data);
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void comet_timer(unsigned long data);
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/* tulip_core.c */
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extern int tulip_debug;
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extern const char * const medianame[];
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extern const char tulip_media_cap[];
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extern struct tulip_chip_table tulip_tbl[];
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void oom_timer(unsigned long data);
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extern u8 t21040_csr13[];
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static inline void tulip_start_rxtx(struct tulip_private *tp)
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{
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void __iomem *ioaddr = tp->base_addr;
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iowrite32(tp->csr6 | RxTx, ioaddr + CSR6);
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barrier();
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(void) ioread32(ioaddr + CSR6); /* mmio sync */
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}
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static inline void tulip_stop_rxtx(struct tulip_private *tp)
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{
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void __iomem *ioaddr = tp->base_addr;
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u32 csr6 = ioread32(ioaddr + CSR6);
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if (csr6 & RxTx) {
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unsigned i=1300/10;
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iowrite32(csr6 & ~RxTx, ioaddr + CSR6);
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barrier();
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/* wait until in-flight frame completes.
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* Max time @ 10BT: 1500*8b/10Mbps == 1200us (+ 100us margin)
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* Typically expect this loop to end in < 50 us on 100BT.
|
|
*/
|
|
while (--i && (ioread32(ioaddr + CSR5) & (CSR5_TS|CSR5_RS)))
|
|
udelay(10);
|
|
|
|
if (!i)
|
|
printk(KERN_DEBUG "%s: tulip_stop_rxtx() failed"
|
|
" (CSR5 0x%x CSR6 0x%x)\n",
|
|
pci_name(tp->pdev),
|
|
ioread32(ioaddr + CSR5),
|
|
ioread32(ioaddr + CSR6));
|
|
}
|
|
}
|
|
|
|
static inline void tulip_restart_rxtx(struct tulip_private *tp)
|
|
{
|
|
tulip_stop_rxtx(tp);
|
|
udelay(5);
|
|
tulip_start_rxtx(tp);
|
|
}
|
|
|
|
static inline void tulip_tx_timeout_complete(struct tulip_private *tp, void __iomem *ioaddr)
|
|
{
|
|
/* Stop and restart the chip's Tx processes. */
|
|
tulip_restart_rxtx(tp);
|
|
/* Trigger an immediate transmit demand. */
|
|
iowrite32(0, ioaddr + CSR1);
|
|
|
|
tp->stats.tx_errors++;
|
|
}
|
|
|
|
#endif /* __NET_TULIP_H__ */
|
|
|