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98 lines
3.3 KiB
98 lines
3.3 KiB
/* $Id: iflash.h,v 1.2 2000/11/13 18:01:54 dwmw2 Exp $ */
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#ifndef __MTD_IFLASH_H__
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#define __MTD_IFLASH_H__
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/* Extended CIS registers for Series 2 and 2+ cards */
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/* The registers are all offsets from 0x4000 */
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#define CISREG_CSR 0x0100
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#define CISREG_WP 0x0104
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#define CISREG_RDYBSY 0x0140
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/* Extended CIS registers for Series 2 cards */
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#define CISREG_SLEEP 0x0118
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#define CISREG_RDY_MASK 0x0120
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#define CISREG_RDY_STATUS 0x0130
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/* Extended CIS registers for Series 2+ cards */
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#define CISREG_VCR 0x010c
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/* Card Status Register */
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#define CSR_SRESET 0x20 /* Soft reset */
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#define CSR_CMWP 0x10 /* Common memory write protect */
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#define CSR_PWRDOWN 0x08 /* Power down status */
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#define CSR_CISWP 0x04 /* Common memory CIS WP */
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#define CSR_WP 0x02 /* Mechanical write protect */
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#define CSR_READY 0x01 /* Ready/busy status */
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/* Write Protection Register */
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#define WP_BLKEN 0x04 /* Enable block locking */
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#define WP_CMWP 0x02 /* Common memory write protect */
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#define WP_CISWP 0x01 /* Common memory CIS WP */
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/* Voltage Control Register */
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#define VCR_VCC_LEVEL 0x80 /* 0 = 5V, 1 = 3.3V */
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#define VCR_VPP_VALID 0x02 /* Vpp Valid */
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#define VCR_VPP_GEN 0x01 /* Integrated Vpp generator */
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/* Ready/Busy Mode Register */
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#define RDYBSY_RACK 0x02 /* Ready acknowledge */
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#define RDYBSY_MODE 0x01 /* 1 = high performance */
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#define LOW(x) ((x) & 0xff)
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/* 28F008SA-Compatible Command Set */
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#define IF_READ_ARRAY 0xffff
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#define IF_INTEL_ID 0x9090
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#define IF_READ_CSR 0x7070
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#define IF_CLEAR_CSR 0x5050
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#define IF_WRITE 0x4040
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#define IF_BLOCK_ERASE 0x2020
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#define IF_ERASE_SUSPEND 0xb0b0
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#define IF_CONFIRM 0xd0d0
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/* 28F016SA Performance Enhancement Commands */
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#define IF_READ_PAGE 0x7575
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#define IF_PAGE_SWAP 0x7272
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#define IF_SINGLE_LOAD 0x7474
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#define IF_SEQ_LOAD 0xe0e0
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#define IF_PAGE_WRITE 0x0c0c
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#define IF_RDY_MODE 0x9696
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#define IF_RDY_LEVEL 0x0101
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#define IF_RDY_PULSE_WRITE 0x0202
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#define IF_RDY_PULSE_ERASE 0x0303
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#define IF_RDY_DISABLE 0x0404
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#define IF_LOCK_BLOCK 0x7777
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#define IF_UPLOAD_STATUS 0x9797
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#define IF_READ_ESR 0x7171
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#define IF_ERASE_UNLOCKED 0xa7a7
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#define IF_SLEEP 0xf0f0
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#define IF_ABORT 0x8080
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#define IF_UPLOAD_DEVINFO 0x9999
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/* Definitions for Compatible Status Register */
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#define CSR_WR_READY 0x8080 /* Write state machine status */
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#define CSR_ERA_SUSPEND 0x4040 /* Erase suspend status */
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#define CSR_ERA_ERR 0x2020 /* Erase status */
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#define CSR_WR_ERR 0x1010 /* Data write status */
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#define CSR_VPP_LOW 0x0808 /* Vpp status */
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/* Definitions for Global Status Register */
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#define GSR_WR_READY 0x8080 /* Write state machine status */
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#define GSR_OP_SUSPEND 0x4040 /* Operation suspend status */
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#define GSR_OP_ERR 0x2020 /* Device operation status */
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#define GSR_SLEEP 0x1010 /* Device sleep status */
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#define GSR_QUEUE_FULL 0x0808 /* Queue status */
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#define GSR_PAGE_AVAIL 0x0404 /* Page buffer available status */
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#define GSR_PAGE_READY 0x0202 /* Page buffer status */
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#define GSR_PAGE_SELECT 0x0101 /* Page buffer select status */
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/* Definitions for Block Status Register */
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#define BSR_READY 0x8080 /* Block status */
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#define BSR_UNLOCK 0x4040 /* Block lock status */
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#define BSR_FAILED 0x2020 /* Block operation status */
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#define BSR_ABORTED 0x1010 /* Operation abort status */
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#define BSR_QUEUE_FULL 0x0808 /* Queue status */
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#define BSR_VPP_LOW 0x0404 /* Vpp status */
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#endif /* __MTD_IFLASH_H__ */
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