You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

Paul Mundt 8263a67e16 sh: Support for extended ASIDs on PTEAEX-capable SH-X3 cores. ... This adds support for extended ASIDs (up to 16-bits) on newer SH-X3 cores that implement the PTAEX register and respective functionality. Presently only the 65nm SH7786 (90nm only supports legacy 8-bit ASIDs). The main change is in how the PTE is written out when loading the entry in to the TLB, as well as in how the TLB entry is selectively flushed. While SH-X2 extended mode splits out the memory-mapped U and I-TLB data arrays for extra bits, extended ASID mode splits out the address arrays. While we don't use the memory-mapped data array access, the address array accesses are necessary for selective TLB flushes, so these are implemented newly and replace the generic SH-4 implementation. With this, TLB flushes in switch_mm() are almost non-existent on newer parts. Signed-off-by: Paul Mundt <lethal@linux-sh.org>		16 years ago
..
irq	…
sh2	…
sh2a	…
sh3	…
sh4	sh: Support for extended ASIDs on PTEAEX-capable SH-X3 cores.	16 years ago
sh4a	sh: Consolidate SH-Mobile CPU code in arch/sh/kernel/cpu/shmobile/.	16 years ago
sh5	…
shmobile	sh: Consolidate SH-Mobile CPU code in arch/sh/kernel/cpu/shmobile/.	16 years ago
Makefile	sh: Consolidate SH-Mobile CPU code in arch/sh/kernel/cpu/shmobile/.	16 years ago
adc.c	…
clock.c	sh: clkfwk: Safer resume from hibernation.	16 years ago
init.c	…
ubc.S	…