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#ifndef __ASM_SH_CPU_SH5_RTC_H
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#define __ASM_SH_CPU_SH5_RTC_H
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#define rtc_reg_size sizeof(u32)
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#define RTC_BIT_INVERTED 0 /* The SH-5 RTC is surprisingly sane! */
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#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR
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#endif /* __ASM_SH_CPU_SH5_RTC_H */
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