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34 lines
1.5 KiB
34 lines
1.5 KiB
#ifndef __ASM_CPU_SH2A_CACHEFLUSH_H
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#define __ASM_CPU_SH2A_CACHEFLUSH_H
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/*
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* Cache flushing:
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*
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* - flush_cache_all() flushes entire cache
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* - flush_cache_mm(mm) flushes the specified mm context's cache lines
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* - flush_cache_dup mm(mm) handles cache flushing when forking
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* - flush_cache_page(mm, vmaddr, pfn) flushes a single page
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* - flush_cache_range(vma, start, end) flushes a range of pages
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*
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* - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
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* - flush_icache_range(start, end) flushes(invalidates) a range for icache
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* - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
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*
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* Caches are indexed (effectively) by physical address on SH-2, so
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* we don't need them.
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*/
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#define flush_cache_all() do { } while (0)
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#define flush_cache_mm(mm) do { } while (0)
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#define flush_cache_dup_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) do { } while (0)
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#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
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#define flush_dcache_page(page) do { } while (0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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void flush_icache_range(unsigned long start, unsigned long end);
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#define flush_icache_page(vma,pg) do { } while (0)
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#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
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#define flush_cache_sigtramp(vaddr) do { } while (0)
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#define p3_cache_init() do { } while (0)
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#endif /* __ASM_CPU_SH2A_CACHEFLUSH_H */
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