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173 lines
3.8 KiB
173 lines
3.8 KiB
/*
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* sc-rm7k.c: RM7000 cache management functions.
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*
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* Copyright (C) 1997, 2001, 2003, 2004 Ralf Baechle (ralf@linux-mips.org)
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*/
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#undef DEBUG
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/bitops.h>
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#include <asm/addrspace.h>
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#include <asm/bcache.h>
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#include <asm/cacheops.h>
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#include <asm/mipsregs.h>
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#include <asm/processor.h>
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#include <asm/cacheflush.h> /* for run_uncached() */
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/* Primary cache parameters. */
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#define sc_lsize 32
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#define tc_pagesize (32*128)
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/* Secondary cache parameters. */
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#define scache_size (256*1024) /* Fixed to 256KiB on RM7000 */
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extern unsigned long icache_way_size, dcache_way_size;
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#include <asm/r4kcache.h>
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int rm7k_tcache_enabled;
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/*
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* Writeback and invalidate the primary cache dcache before DMA.
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* (XXX These need to be fixed ...)
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*/
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static void rm7k_sc_wback_inv(unsigned long addr, unsigned long size)
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{
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unsigned long end, a;
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pr_debug("rm7k_sc_wback_inv[%08lx,%08lx]", addr, size);
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/* Catch bad driver code */
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BUG_ON(size == 0);
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blast_scache_range(addr, addr + size);
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if (!rm7k_tcache_enabled)
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return;
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a = addr & ~(tc_pagesize - 1);
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end = (addr + size - 1) & ~(tc_pagesize - 1);
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while(1) {
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invalidate_tcache_page(a); /* Page_Invalidate_T */
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if (a == end)
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break;
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a += tc_pagesize;
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}
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}
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static void rm7k_sc_inv(unsigned long addr, unsigned long size)
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{
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unsigned long end, a;
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pr_debug("rm7k_sc_inv[%08lx,%08lx]", addr, size);
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/* Catch bad driver code */
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BUG_ON(size == 0);
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blast_inv_scache_range(addr, addr + size);
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if (!rm7k_tcache_enabled)
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return;
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a = addr & ~(tc_pagesize - 1);
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end = (addr + size - 1) & ~(tc_pagesize - 1);
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while(1) {
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invalidate_tcache_page(a); /* Page_Invalidate_T */
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if (a == end)
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break;
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a += tc_pagesize;
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}
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}
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/*
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* This function is executed in uncached address space.
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*/
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static __cpuinit void __rm7k_sc_enable(void)
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{
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int i;
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set_c0_config(RM7K_CONF_SE);
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write_c0_taglo(0);
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write_c0_taghi(0);
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for (i = 0; i < scache_size; i += sc_lsize) {
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__asm__ __volatile__ (
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".set noreorder\n\t"
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".set mips3\n\t"
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"cache %1, (%0)\n\t"
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".set mips0\n\t"
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".set reorder"
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:
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: "r" (CKSEG0ADDR(i)), "i" (Index_Store_Tag_SD));
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}
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}
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static __cpuinit void rm7k_sc_enable(void)
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{
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if (read_c0_config() & RM7K_CONF_SE)
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return;
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printk(KERN_INFO "Enabling secondary cache...\n");
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run_uncached(__rm7k_sc_enable);
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}
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static void rm7k_sc_disable(void)
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{
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clear_c0_config(RM7K_CONF_SE);
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}
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struct bcache_ops rm7k_sc_ops = {
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.bc_enable = rm7k_sc_enable,
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.bc_disable = rm7k_sc_disable,
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.bc_wback_inv = rm7k_sc_wback_inv,
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.bc_inv = rm7k_sc_inv
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};
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void __cpuinit rm7k_sc_init(void)
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{
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struct cpuinfo_mips *c = ¤t_cpu_data;
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unsigned int config = read_c0_config();
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if ((config & RM7K_CONF_SC))
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return;
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c->scache.linesz = sc_lsize;
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c->scache.ways = 4;
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c->scache.waybit= __ffs(scache_size / c->scache.ways);
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c->scache.waysize = scache_size / c->scache.ways;
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c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
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printk(KERN_INFO "Secondary cache size %dK, linesize %d bytes.\n",
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(scache_size >> 10), sc_lsize);
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if (!(config & RM7K_CONF_SE))
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rm7k_sc_enable();
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/*
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* While we're at it let's deal with the tertiary cache.
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*/
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if (!(config & RM7K_CONF_TC)) {
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/*
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* We can't enable the L3 cache yet. There may be board-specific
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* magic necessary to turn it on, and blindly asking the CPU to
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* start using it would may give cache errors.
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*
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* Also, board-specific knowledge may allow us to use the
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* CACHE Flash_Invalidate_T instruction if the tag RAM supports
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* it, and may specify the size of the L3 cache so we don't have
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* to probe it.
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*/
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printk(KERN_INFO "Tertiary cache present, %s enabled\n",
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(config & RM7K_CONF_TE) ? "already" : "not (yet)");
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if ((config & RM7K_CONF_TE))
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rm7k_tcache_enabled = 1;
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}
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bcops = &rm7k_sc_ops;
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}
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