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433 lines
12 KiB
433 lines
12 KiB
/*
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* PCI Virtual Channel support
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*
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* Copyright (C) 2013 Red Hat, Inc. All rights reserved.
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* Author: Alex Williamson <alex.williamson@redhat.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/pci_regs.h>
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#include <linux/types.h>
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/**
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* pci_vc_save_restore_dwords - Save or restore a series of dwords
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* @dev: device
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* @pos: starting config space position
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* @buf: buffer to save to or restore from
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* @dwords: number of dwords to save/restore
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* @save: whether to save or restore
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*/
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static void pci_vc_save_restore_dwords(struct pci_dev *dev, int pos,
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u32 *buf, int dwords, bool save)
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{
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int i;
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for (i = 0; i < dwords; i++, buf++) {
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if (save)
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pci_read_config_dword(dev, pos + (i * 4), buf);
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else
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pci_write_config_dword(dev, pos + (i * 4), *buf);
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}
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}
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/**
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* pci_vc_load_arb_table - load and wait for VC arbitration table
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* @dev: device
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* @pos: starting position of VC capability (VC/VC9/MFVC)
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*
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* Set Load VC Arbitration Table bit requesting hardware to apply the VC
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* Arbitration Table (previously loaded). When the VC Arbitration Table
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* Status clears, hardware has latched the table into VC arbitration logic.
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*/
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static void pci_vc_load_arb_table(struct pci_dev *dev, int pos)
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{
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u16 ctrl;
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pci_read_config_word(dev, pos + PCI_VC_PORT_CTRL, &ctrl);
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pci_write_config_word(dev, pos + PCI_VC_PORT_CTRL,
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ctrl | PCI_VC_PORT_CTRL_LOAD_TABLE);
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if (pci_wait_for_pending(dev, pos + PCI_VC_PORT_STATUS,
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PCI_VC_PORT_STATUS_TABLE))
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return;
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dev_err(&dev->dev, "VC arbitration table failed to load\n");
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}
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/**
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* pci_vc_load_port_arb_table - Load and wait for VC port arbitration table
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* @dev: device
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* @pos: starting position of VC capability (VC/VC9/MFVC)
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* @res: VC resource number, ie. VCn (0-7)
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*
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* Set Load Port Arbitration Table bit requesting hardware to apply the Port
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* Arbitration Table (previously loaded). When the Port Arbitration Table
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* Status clears, hardware has latched the table into port arbitration logic.
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*/
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static void pci_vc_load_port_arb_table(struct pci_dev *dev, int pos, int res)
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{
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int ctrl_pos, status_pos;
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u32 ctrl;
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ctrl_pos = pos + PCI_VC_RES_CTRL + (res * PCI_CAP_VC_PER_VC_SIZEOF);
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status_pos = pos + PCI_VC_RES_STATUS + (res * PCI_CAP_VC_PER_VC_SIZEOF);
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pci_read_config_dword(dev, ctrl_pos, &ctrl);
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pci_write_config_dword(dev, ctrl_pos,
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ctrl | PCI_VC_RES_CTRL_LOAD_TABLE);
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if (pci_wait_for_pending(dev, status_pos, PCI_VC_RES_STATUS_TABLE))
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return;
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dev_err(&dev->dev, "VC%d port arbitration table failed to load\n", res);
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}
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/**
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* pci_vc_enable - Enable virtual channel
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* @dev: device
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* @pos: starting position of VC capability (VC/VC9/MFVC)
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* @res: VC res number, ie. VCn (0-7)
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*
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* A VC is enabled by setting the enable bit in matching resource control
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* registers on both sides of a link. We therefore need to find the opposite
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* end of the link. To keep this simple we enable from the downstream device.
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* RC devices do not have an upstream device, nor does it seem that VC9 do
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* (spec is unclear). Once we find the upstream device, match the VC ID to
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* get the correct resource, disable and enable on both ends.
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*/
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static void pci_vc_enable(struct pci_dev *dev, int pos, int res)
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{
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int ctrl_pos, status_pos, id, pos2, evcc, i, ctrl_pos2, status_pos2;
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u32 ctrl, header, cap1, ctrl2;
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struct pci_dev *link = NULL;
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/* Enable VCs from the downstream device */
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if (!dev->has_secondary_link)
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return;
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ctrl_pos = pos + PCI_VC_RES_CTRL + (res * PCI_CAP_VC_PER_VC_SIZEOF);
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status_pos = pos + PCI_VC_RES_STATUS + (res * PCI_CAP_VC_PER_VC_SIZEOF);
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pci_read_config_dword(dev, ctrl_pos, &ctrl);
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id = ctrl & PCI_VC_RES_CTRL_ID;
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pci_read_config_dword(dev, pos, &header);
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/* If there is no opposite end of the link, skip to enable */
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if (PCI_EXT_CAP_ID(header) == PCI_EXT_CAP_ID_VC9 ||
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pci_is_root_bus(dev->bus))
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goto enable;
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pos2 = pci_find_ext_capability(dev->bus->self, PCI_EXT_CAP_ID_VC);
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if (!pos2)
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goto enable;
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pci_read_config_dword(dev->bus->self, pos2 + PCI_VC_PORT_CAP1, &cap1);
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evcc = cap1 & PCI_VC_CAP1_EVCC;
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/* VC0 is hardwired enabled, so we can start with 1 */
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for (i = 1; i < evcc + 1; i++) {
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ctrl_pos2 = pos2 + PCI_VC_RES_CTRL +
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(i * PCI_CAP_VC_PER_VC_SIZEOF);
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status_pos2 = pos2 + PCI_VC_RES_STATUS +
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(i * PCI_CAP_VC_PER_VC_SIZEOF);
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pci_read_config_dword(dev->bus->self, ctrl_pos2, &ctrl2);
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if ((ctrl2 & PCI_VC_RES_CTRL_ID) == id) {
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link = dev->bus->self;
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break;
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}
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}
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if (!link)
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goto enable;
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/* Disable if enabled */
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if (ctrl2 & PCI_VC_RES_CTRL_ENABLE) {
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ctrl2 &= ~PCI_VC_RES_CTRL_ENABLE;
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pci_write_config_dword(link, ctrl_pos2, ctrl2);
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}
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/* Enable on both ends */
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ctrl2 |= PCI_VC_RES_CTRL_ENABLE;
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pci_write_config_dword(link, ctrl_pos2, ctrl2);
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enable:
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ctrl |= PCI_VC_RES_CTRL_ENABLE;
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pci_write_config_dword(dev, ctrl_pos, ctrl);
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if (!pci_wait_for_pending(dev, status_pos, PCI_VC_RES_STATUS_NEGO))
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dev_err(&dev->dev, "VC%d negotiation stuck pending\n", id);
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if (link && !pci_wait_for_pending(link, status_pos2,
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PCI_VC_RES_STATUS_NEGO))
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dev_err(&link->dev, "VC%d negotiation stuck pending\n", id);
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}
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/**
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* pci_vc_do_save_buffer - Size, save, or restore VC state
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* @dev: device
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* @pos: starting position of VC capability (VC/VC9/MFVC)
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* @save_state: buffer for save/restore
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* @name: for error message
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* @save: if provided a buffer, this indicates what to do with it
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*
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* Walking Virtual Channel config space to size, save, or restore it
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* is complicated, so we do it all from one function to reduce code and
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* guarantee ordering matches in the buffer. When called with NULL
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* @save_state, return the size of the necessary save buffer. When called
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* with a non-NULL @save_state, @save determines whether we save to the
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* buffer or restore from it.
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*/
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static int pci_vc_do_save_buffer(struct pci_dev *dev, int pos,
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struct pci_cap_saved_state *save_state,
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bool save)
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{
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u32 cap1;
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char evcc, lpevcc, parb_size;
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int i, len = 0;
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u8 *buf = save_state ? (u8 *)save_state->cap.data : NULL;
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/* Sanity check buffer size for save/restore */
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if (buf && save_state->cap.size !=
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pci_vc_do_save_buffer(dev, pos, NULL, save)) {
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dev_err(&dev->dev,
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"VC save buffer size does not match @0x%x\n", pos);
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return -ENOMEM;
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}
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pci_read_config_dword(dev, pos + PCI_VC_PORT_CAP1, &cap1);
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/* Extended VC Count (not counting VC0) */
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evcc = cap1 & PCI_VC_CAP1_EVCC;
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/* Low Priority Extended VC Count (not counting VC0) */
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lpevcc = (cap1 & PCI_VC_CAP1_LPEVCC) >> 4;
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/* Port Arbitration Table Entry Size (bits) */
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parb_size = 1 << ((cap1 & PCI_VC_CAP1_ARB_SIZE) >> 10);
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/*
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* Port VC Control Register contains VC Arbitration Select, which
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* cannot be modified when more than one LPVC is in operation. We
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* therefore save/restore it first, as only VC0 should be enabled
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* after device reset.
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*/
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if (buf) {
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if (save)
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pci_read_config_word(dev, pos + PCI_VC_PORT_CTRL,
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(u16 *)buf);
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else
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pci_write_config_word(dev, pos + PCI_VC_PORT_CTRL,
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*(u16 *)buf);
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buf += 4;
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}
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len += 4;
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/*
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* If we have any Low Priority VCs and a VC Arbitration Table Offset
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* in Port VC Capability Register 2 then save/restore it next.
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*/
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if (lpevcc) {
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u32 cap2;
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int vcarb_offset;
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pci_read_config_dword(dev, pos + PCI_VC_PORT_CAP2, &cap2);
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vcarb_offset = ((cap2 & PCI_VC_CAP2_ARB_OFF) >> 24) * 16;
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if (vcarb_offset) {
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int size, vcarb_phases = 0;
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if (cap2 & PCI_VC_CAP2_128_PHASE)
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vcarb_phases = 128;
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else if (cap2 & PCI_VC_CAP2_64_PHASE)
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vcarb_phases = 64;
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else if (cap2 & PCI_VC_CAP2_32_PHASE)
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vcarb_phases = 32;
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/* Fixed 4 bits per phase per lpevcc (plus VC0) */
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size = ((lpevcc + 1) * vcarb_phases * 4) / 8;
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if (size && buf) {
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pci_vc_save_restore_dwords(dev,
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pos + vcarb_offset,
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(u32 *)buf,
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size / 4, save);
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/*
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* On restore, we need to signal hardware to
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* re-load the VC Arbitration Table.
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*/
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if (!save)
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pci_vc_load_arb_table(dev, pos);
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buf += size;
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}
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len += size;
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}
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}
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/*
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* In addition to each VC Resource Control Register, we may have a
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* Port Arbitration Table attached to each VC. The Port Arbitration
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* Table Offset in each VC Resource Capability Register tells us if
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* it exists. The entry size is global from the Port VC Capability
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* Register1 above. The number of phases is determined per VC.
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*/
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for (i = 0; i < evcc + 1; i++) {
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u32 cap;
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int parb_offset;
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pci_read_config_dword(dev, pos + PCI_VC_RES_CAP +
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(i * PCI_CAP_VC_PER_VC_SIZEOF), &cap);
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parb_offset = ((cap & PCI_VC_RES_CAP_ARB_OFF) >> 24) * 16;
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if (parb_offset) {
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int size, parb_phases = 0;
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if (cap & PCI_VC_RES_CAP_256_PHASE)
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parb_phases = 256;
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else if (cap & (PCI_VC_RES_CAP_128_PHASE |
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PCI_VC_RES_CAP_128_PHASE_TB))
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parb_phases = 128;
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else if (cap & PCI_VC_RES_CAP_64_PHASE)
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parb_phases = 64;
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else if (cap & PCI_VC_RES_CAP_32_PHASE)
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parb_phases = 32;
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size = (parb_size * parb_phases) / 8;
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if (size && buf) {
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pci_vc_save_restore_dwords(dev,
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pos + parb_offset,
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(u32 *)buf,
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size / 4, save);
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buf += size;
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}
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len += size;
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}
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/* VC Resource Control Register */
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if (buf) {
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int ctrl_pos = pos + PCI_VC_RES_CTRL +
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(i * PCI_CAP_VC_PER_VC_SIZEOF);
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if (save)
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pci_read_config_dword(dev, ctrl_pos,
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(u32 *)buf);
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else {
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u32 tmp, ctrl = *(u32 *)buf;
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/*
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* For an FLR case, the VC config may remain.
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* Preserve enable bit, restore the rest.
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*/
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pci_read_config_dword(dev, ctrl_pos, &tmp);
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tmp &= PCI_VC_RES_CTRL_ENABLE;
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tmp |= ctrl & ~PCI_VC_RES_CTRL_ENABLE;
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pci_write_config_dword(dev, ctrl_pos, tmp);
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/* Load port arbitration table if used */
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if (ctrl & PCI_VC_RES_CTRL_ARB_SELECT)
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pci_vc_load_port_arb_table(dev, pos, i);
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/* Re-enable if needed */
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if ((ctrl ^ tmp) & PCI_VC_RES_CTRL_ENABLE)
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pci_vc_enable(dev, pos, i);
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}
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buf += 4;
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}
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len += 4;
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}
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return buf ? 0 : len;
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}
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static struct {
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u16 id;
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const char *name;
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} vc_caps[] = { { PCI_EXT_CAP_ID_MFVC, "MFVC" },
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{ PCI_EXT_CAP_ID_VC, "VC" },
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{ PCI_EXT_CAP_ID_VC9, "VC9" } };
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/**
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* pci_save_vc_state - Save VC state to pre-allocate save buffer
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* @dev: device
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*
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* For each type of VC capability, VC/VC9/MFVC, find the capability and
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* save it to the pre-allocated save buffer.
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*/
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int pci_save_vc_state(struct pci_dev *dev)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(vc_caps); i++) {
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int pos, ret;
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struct pci_cap_saved_state *save_state;
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pos = pci_find_ext_capability(dev, vc_caps[i].id);
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if (!pos)
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continue;
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save_state = pci_find_saved_ext_cap(dev, vc_caps[i].id);
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if (!save_state) {
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dev_err(&dev->dev, "%s buffer not found in %s\n",
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vc_caps[i].name, __func__);
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return -ENOMEM;
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}
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ret = pci_vc_do_save_buffer(dev, pos, save_state, true);
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if (ret) {
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dev_err(&dev->dev, "%s save unsuccessful %s\n",
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vc_caps[i].name, __func__);
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return ret;
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}
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}
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return 0;
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}
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/**
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* pci_restore_vc_state - Restore VC state from save buffer
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* @dev: device
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*
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* For each type of VC capability, VC/VC9/MFVC, find the capability and
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* restore it from the previously saved buffer.
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*/
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void pci_restore_vc_state(struct pci_dev *dev)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(vc_caps); i++) {
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int pos;
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struct pci_cap_saved_state *save_state;
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pos = pci_find_ext_capability(dev, vc_caps[i].id);
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save_state = pci_find_saved_ext_cap(dev, vc_caps[i].id);
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if (!save_state || !pos)
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continue;
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pci_vc_do_save_buffer(dev, pos, save_state, false);
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}
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}
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/**
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* pci_allocate_vc_save_buffers - Allocate save buffers for VC caps
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* @dev: device
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*
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* For each type of VC capability, VC/VC9/MFVC, find the capability, size
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* it, and allocate a buffer for save/restore.
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*/
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void pci_allocate_vc_save_buffers(struct pci_dev *dev)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(vc_caps); i++) {
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int len, pos = pci_find_ext_capability(dev, vc_caps[i].id);
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if (!pos)
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continue;
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len = pci_vc_do_save_buffer(dev, pos, NULL, false);
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if (pci_add_ext_cap_save_buffer(dev, vc_caps[i].id, len))
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dev_err(&dev->dev,
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"unable to preallocate %s save buffer\n",
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vc_caps[i].name);
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}
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}
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