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143 lines
3.6 KiB
143 lines
3.6 KiB
/*
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* Freescale eSDHC controller driver.
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*
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* Copyright (c) 2007 Freescale Semiconductor, Inc.
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* Copyright (c) 2009 MontaVista Software, Inc.
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*
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* Authors: Xiaobo Xie <X.Xie@freescale.com>
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*/
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/mmc/host.h>
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#include "sdhci-of.h"
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#include "sdhci.h"
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/*
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* Ops and quirks for the Freescale eSDHC controller.
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*/
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#define ESDHC_DMA_SYSCTL 0x40c
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#define ESDHC_DMA_SNOOP 0x00000040
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#define ESDHC_SYSTEM_CONTROL 0x2c
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#define ESDHC_CLOCK_MASK 0x0000fff0
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#define ESDHC_PREDIV_SHIFT 8
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#define ESDHC_DIVIDER_SHIFT 4
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#define ESDHC_CLOCK_PEREN 0x00000004
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#define ESDHC_CLOCK_HCKEN 0x00000002
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#define ESDHC_CLOCK_IPGEN 0x00000001
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#define ESDHC_HOST_CONTROL_RES 0x05
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static u16 esdhc_readw(struct sdhci_host *host, int reg)
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{
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u16 ret;
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if (unlikely(reg == SDHCI_HOST_VERSION))
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ret = in_be16(host->ioaddr + reg);
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else
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ret = sdhci_be32bs_readw(host, reg);
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return ret;
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}
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static void esdhc_writew(struct sdhci_host *host, u16 val, int reg)
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{
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if (reg == SDHCI_BLOCK_SIZE) {
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/*
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* Two last DMA bits are reserved, and first one is used for
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* non-standard blksz of 4096 bytes that we don't support
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* yet. So clear the DMA boundary bits.
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*/
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val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
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}
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sdhci_be32bs_writew(host, val, reg);
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}
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static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg)
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{
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/* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */
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if (reg == SDHCI_HOST_CONTROL)
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val &= ~ESDHC_HOST_CONTROL_RES;
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sdhci_be32bs_writeb(host, val, reg);
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}
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static void esdhc_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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int pre_div = 2;
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int div = 1;
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clrbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN |
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ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK);
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if (clock == 0)
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goto out;
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while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
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pre_div *= 2;
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while (host->max_clk / pre_div / div > clock && div < 16)
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div++;
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dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
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clock, host->max_clk / pre_div / div);
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pre_div >>= 1;
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div--;
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setbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN |
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ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN |
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div << ESDHC_DIVIDER_SHIFT | pre_div << ESDHC_PREDIV_SHIFT);
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mdelay(100);
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out:
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host->clock = clock;
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}
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static int esdhc_enable_dma(struct sdhci_host *host)
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{
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setbits32(host->ioaddr + ESDHC_DMA_SYSCTL, ESDHC_DMA_SNOOP);
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return 0;
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}
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static unsigned int esdhc_get_max_clock(struct sdhci_host *host)
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{
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struct sdhci_of_host *of_host = sdhci_priv(host);
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return of_host->clock;
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}
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static unsigned int esdhc_get_min_clock(struct sdhci_host *host)
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{
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struct sdhci_of_host *of_host = sdhci_priv(host);
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return of_host->clock / 256 / 16;
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}
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struct sdhci_of_data sdhci_esdhc = {
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.quirks = SDHCI_QUIRK_FORCE_BLK_SZ_2048 |
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SDHCI_QUIRK_BROKEN_CARD_DETECTION |
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SDHCI_QUIRK_NO_BUSY_IRQ |
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SDHCI_QUIRK_NONSTANDARD_CLOCK |
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SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
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SDHCI_QUIRK_PIO_NEEDS_DELAY |
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SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET |
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SDHCI_QUIRK_NO_CARD_NO_RESET,
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.ops = {
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.readl = sdhci_be32bs_readl,
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.readw = esdhc_readw,
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.readb = sdhci_be32bs_readb,
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.writel = sdhci_be32bs_writel,
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.writew = esdhc_writew,
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.writeb = esdhc_writeb,
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.set_clock = esdhc_set_clock,
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.enable_dma = esdhc_enable_dma,
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.get_max_clock = esdhc_get_max_clock,
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.get_min_clock = esdhc_get_min_clock,
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},
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};
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