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167 lines
4.2 KiB
167 lines
4.2 KiB
config PPC_CELL
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bool
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default n
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config PPC_CELL_COMMON
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bool
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select PPC_CELL
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select PPC_DCR_MMIO
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select PPC_INDIRECT_IO
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select PPC_NATIVE
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select PPC_RTAS
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config PPC_CELL_NATIVE
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bool
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select PPC_CELL_COMMON
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select MPIC
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select IBM_NEW_EMAC_EMAC4
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select IBM_NEW_EMAC_RGMII
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select IBM_NEW_EMAC_ZMII #test only
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select IBM_NEW_EMAC_TAH #test only
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default n
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config PPC_IBM_CELL_BLADE
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bool "IBM Cell Blade"
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depends on PPC64 && PPC_BOOK3S
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select PPC_CELL_NATIVE
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select PPC_OF_PLATFORM_PCI
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select PCI
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select MMIO_NVRAM
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select PPC_UDBG_16550
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select UDBG_RTAS_CONSOLE
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config PPC_CELLEB
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bool "Toshiba's Cell Reference Set 'Celleb' Architecture"
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depends on PPC64 && PPC_BOOK3S
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select PPC_CELL_NATIVE
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select PPC_OF_PLATFORM_PCI
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select PCI
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select HAS_TXX9_SERIAL
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select PPC_UDBG_BEAT
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select USB_OHCI_BIG_ENDIAN_MMIO
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select USB_EHCI_BIG_ENDIAN_MMIO
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config PPC_CELL_QPACE
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bool "IBM Cell - QPACE"
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depends on PPC64 && PPC_BOOK3S
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select PPC_CELL_COMMON
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config AXON_MSI
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bool
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depends on PPC_IBM_CELL_BLADE && PCI_MSI
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default y
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menu "Cell Broadband Engine options"
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depends on PPC_CELL
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config SPU_FS
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tristate "SPU file system"
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default m
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depends on PPC_CELL
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select SPU_BASE
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select MEMORY_HOTPLUG
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help
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The SPU file system is used to access Synergistic Processing
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Units on machines implementing the Broadband Processor
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Architecture.
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config SPU_FS_64K_LS
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bool "Use 64K pages to map SPE local store"
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# we depend on PPC_MM_SLICES for now rather than selecting
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# it because we depend on hugetlbfs hooks being present. We
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# will fix that when the generic code has been improved to
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# not require hijacking hugetlbfs hooks.
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depends on SPU_FS && PPC_MM_SLICES && !PPC_64K_PAGES
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default y
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select PPC_HAS_HASH_64K
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help
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This option causes SPE local stores to be mapped in process
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address spaces using 64K pages while the rest of the kernel
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uses 4K pages. This can improve performances of applications
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using multiple SPEs by lowering the TLB pressure on them.
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config SPU_TRACE
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tristate "SPU event tracing support"
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depends on SPU_FS && MARKERS
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help
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This option allows reading a trace of spu-related events through
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the sputrace file in procfs.
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config SPU_BASE
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bool
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default n
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config CBE_RAS
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bool "RAS features for bare metal Cell BE"
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depends on PPC_CELL_NATIVE
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default y
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config PPC_IBM_CELL_RESETBUTTON
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bool "IBM Cell Blade Pinhole reset button"
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depends on CBE_RAS && PPC_IBM_CELL_BLADE
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default y
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help
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Support Pinhole Resetbutton on IBM Cell blades.
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This adds a method to trigger system reset via front panel pinhole button.
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config PPC_IBM_CELL_POWERBUTTON
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tristate "IBM Cell Blade power button"
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depends on PPC_IBM_CELL_BLADE && INPUT_EVDEV
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default y
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help
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Support Powerbutton on IBM Cell blades.
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This will enable the powerbutton as an input device.
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config CBE_THERM
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tristate "CBE thermal support"
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default m
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depends on CBE_RAS && SPU_BASE
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config CBE_CPUFREQ
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tristate "CBE frequency scaling"
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depends on CBE_RAS && CPU_FREQ
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default m
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help
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This adds the cpufreq driver for Cell BE processors.
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For details, take a look at <file:Documentation/cpu-freq/>.
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If you don't have such processor, say N
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config CBE_CPUFREQ_PMI_ENABLE
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bool "CBE frequency scaling using PMI interface"
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depends on CBE_CPUFREQ && EXPERIMENTAL
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default n
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help
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Select this, if you want to use the PMI interface
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to switch frequencies. Using PMI, the
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processor will not only be able to run at lower speed,
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but also at lower core voltage.
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config CBE_CPUFREQ_PMI
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tristate
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depends on CBE_CPUFREQ_PMI_ENABLE
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default CBE_CPUFREQ
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config PPC_PMI
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tristate
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default y
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depends on CBE_CPUFREQ_PMI || PPC_IBM_CELL_POWERBUTTON
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help
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PMI (Platform Management Interrupt) is a way to
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communicate with the BMC (Baseboard Management Controller).
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It is used in some IBM Cell blades.
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config CBE_CPUFREQ_SPU_GOVERNOR
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tristate "CBE frequency scaling based on SPU usage"
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depends on SPU_FS && CPU_FREQ
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default m
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help
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This governor checks for spu usage to adjust the cpu frequency.
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If no spu is running on a given cpu, that cpu will be throttled to
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the minimal possible frequency.
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endmenu
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config OPROFILE_CELL
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def_bool y
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depends on PPC_CELL_NATIVE && (OPROFILE = m || OPROFILE = y) && SPU_BASE
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