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Graf Yang 5bc6e3cfe6 Blackfin: add CPLB entries for Core B on-chip L1 SRAM regions ... The Blackfin SMP port was missing CPLB entries for Core B on-chip L1 SRAM regions. Any code that attempted to use these would wrongly crash due to a CPLB miss. Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>		16 years ago
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Makefile	…
cacheinit.c	…
cplbinit.c	Blackfin: add CPLB entries for Core B on-chip L1 SRAM regions	16 years ago
cplbmgr.c	Blackfin: only handle CPLB protection violations when MPU is enabled	16 years ago