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180 lines
6.4 KiB
180 lines
6.4 KiB
/*
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* Atmel PIO2 Port Multiplexer support
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*
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* Copyright (C) 2004-2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ARCH_AVR32_AT32AP_PIO_H__
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#define __ARCH_AVR32_AT32AP_PIO_H__
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/* PIO register offsets */
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#define PIO_PER 0x0000
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#define PIO_PDR 0x0004
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#define PIO_PSR 0x0008
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#define PIO_OER 0x0010
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#define PIO_ODR 0x0014
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#define PIO_OSR 0x0018
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#define PIO_IFER 0x0020
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#define PIO_IFDR 0x0024
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#define PIO_IFSR 0x0028
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#define PIO_SODR 0x0030
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#define PIO_CODR 0x0034
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#define PIO_ODSR 0x0038
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#define PIO_PDSR 0x003c
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#define PIO_IER 0x0040
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#define PIO_IDR 0x0044
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#define PIO_IMR 0x0048
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#define PIO_ISR 0x004c
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#define PIO_MDER 0x0050
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#define PIO_MDDR 0x0054
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#define PIO_MDSR 0x0058
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#define PIO_PUDR 0x0060
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#define PIO_PUER 0x0064
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#define PIO_PUSR 0x0068
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#define PIO_ASR 0x0070
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#define PIO_BSR 0x0074
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#define PIO_ABSR 0x0078
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#define PIO_OWER 0x00a0
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#define PIO_OWDR 0x00a4
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#define PIO_OWSR 0x00a8
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/* Bitfields in PER */
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/* Bitfields in PDR */
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/* Bitfields in PSR */
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/* Bitfields in OER */
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/* Bitfields in ODR */
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/* Bitfields in OSR */
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/* Bitfields in IFER */
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/* Bitfields in IFDR */
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/* Bitfields in IFSR */
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/* Bitfields in SODR */
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/* Bitfields in CODR */
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/* Bitfields in ODSR */
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/* Bitfields in PDSR */
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/* Bitfields in IER */
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/* Bitfields in IDR */
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/* Bitfields in IMR */
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/* Bitfields in ISR */
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/* Bitfields in MDER */
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/* Bitfields in MDDR */
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/* Bitfields in MDSR */
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/* Bitfields in PUDR */
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/* Bitfields in PUER */
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/* Bitfields in PUSR */
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/* Bitfields in ASR */
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/* Bitfields in BSR */
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/* Bitfields in ABSR */
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#define PIO_P0_OFFSET 0
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#define PIO_P0_SIZE 1
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#define PIO_P1_OFFSET 1
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#define PIO_P1_SIZE 1
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#define PIO_P2_OFFSET 2
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#define PIO_P2_SIZE 1
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#define PIO_P3_OFFSET 3
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#define PIO_P3_SIZE 1
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#define PIO_P4_OFFSET 4
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#define PIO_P4_SIZE 1
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#define PIO_P5_OFFSET 5
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#define PIO_P5_SIZE 1
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#define PIO_P6_OFFSET 6
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#define PIO_P6_SIZE 1
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#define PIO_P7_OFFSET 7
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#define PIO_P7_SIZE 1
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#define PIO_P8_OFFSET 8
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#define PIO_P8_SIZE 1
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#define PIO_P9_OFFSET 9
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#define PIO_P9_SIZE 1
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#define PIO_P10_OFFSET 10
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#define PIO_P10_SIZE 1
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#define PIO_P11_OFFSET 11
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#define PIO_P11_SIZE 1
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#define PIO_P12_OFFSET 12
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#define PIO_P12_SIZE 1
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#define PIO_P13_OFFSET 13
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#define PIO_P13_SIZE 1
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#define PIO_P14_OFFSET 14
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#define PIO_P14_SIZE 1
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#define PIO_P15_OFFSET 15
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#define PIO_P15_SIZE 1
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#define PIO_P16_OFFSET 16
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#define PIO_P16_SIZE 1
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#define PIO_P17_OFFSET 17
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#define PIO_P17_SIZE 1
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#define PIO_P18_OFFSET 18
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#define PIO_P18_SIZE 1
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#define PIO_P19_OFFSET 19
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#define PIO_P19_SIZE 1
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#define PIO_P20_OFFSET 20
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#define PIO_P20_SIZE 1
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#define PIO_P21_OFFSET 21
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#define PIO_P21_SIZE 1
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#define PIO_P22_OFFSET 22
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#define PIO_P22_SIZE 1
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#define PIO_P23_OFFSET 23
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#define PIO_P23_SIZE 1
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#define PIO_P24_OFFSET 24
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#define PIO_P24_SIZE 1
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#define PIO_P25_OFFSET 25
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#define PIO_P25_SIZE 1
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#define PIO_P26_OFFSET 26
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#define PIO_P26_SIZE 1
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#define PIO_P27_OFFSET 27
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#define PIO_P27_SIZE 1
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#define PIO_P28_OFFSET 28
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#define PIO_P28_SIZE 1
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#define PIO_P29_OFFSET 29
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#define PIO_P29_SIZE 1
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#define PIO_P30_OFFSET 30
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#define PIO_P30_SIZE 1
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#define PIO_P31_OFFSET 31
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#define PIO_P31_SIZE 1
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/* Bitfields in OWER */
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/* Bitfields in OWDR */
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/* Bitfields in OWSR */
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/* Bit manipulation macros */
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#define PIO_BIT(name) (1 << PIO_##name##_OFFSET)
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#define PIO_BF(name,value) (((value) & ((1 << PIO_##name##_SIZE) - 1)) << PIO_##name##_OFFSET)
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#define PIO_BFEXT(name,value) (((value) >> PIO_##name##_OFFSET) & ((1 << PIO_##name##_SIZE) - 1))
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#define PIO_BFINS(name,value,old) (((old) & ~(((1 << PIO_##name##_SIZE) - 1) << PIO_##name##_OFFSET)) | PIO_BF(name,value))
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/* Register access macros */
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#define pio_readl(port,reg) \
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__raw_readl((port)->regs + PIO_##reg)
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#define pio_writel(port,reg,value) \
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__raw_writel((value), (port)->regs + PIO_##reg)
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void at32_init_pio(struct platform_device *pdev);
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#endif /* __ARCH_AVR32_AT32AP_PIO_H__ */
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