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238 lines
6.0 KiB
238 lines
6.0 KiB
/*
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* arch/ppc/syslib/ibm44x_common.c
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*
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* PPC44x system library
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*
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* Matt Porter <mporter@kernel.crashing.org>
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* Copyright 2002-2005 MontaVista Software Inc.
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*
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* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
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* Copyright (c) 2003, 2004 Zultys Technologies
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/config.h>
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#include <linux/time.h>
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#include <linux/types.h>
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#include <linux/serial.h>
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#include <linux/module.h>
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#include <linux/initrd.h>
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#include <asm/ibm44x.h>
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#include <asm/mmu.h>
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#include <asm/machdep.h>
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#include <asm/time.h>
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#include <asm/ppc4xx_pic.h>
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#include <asm/param.h>
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#include <asm/bootinfo.h>
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#include <asm/ppcboot.h>
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#include <syslib/gen550.h>
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/* Global Variables */
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bd_t __res;
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phys_addr_t fixup_bigphys_addr(phys_addr_t addr, phys_addr_t size)
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{
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phys_addr_t page_4gb = 0;
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/*
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* Trap the least significant 32-bit portions of an
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* address in the 440's 36-bit address space. Fix
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* them up with the appropriate ERPN
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*/
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if ((addr >= PPC44x_IO_LO) && (addr <= PPC44x_IO_HI))
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page_4gb = PPC44x_IO_PAGE;
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else if ((addr >= PPC44x_PCI0CFG_LO) && (addr <= PPC44x_PCI0CFG_HI))
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page_4gb = PPC44x_PCICFG_PAGE;
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#ifdef CONFIG_440SP
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else if ((addr >= PPC44x_PCI1CFG_LO) && (addr <= PPC44x_PCI1CFG_HI))
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page_4gb = PPC44x_PCICFG_PAGE;
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else if ((addr >= PPC44x_PCI2CFG_LO) && (addr <= PPC44x_PCI2CFG_HI))
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page_4gb = PPC44x_PCICFG_PAGE;
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#endif
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else if ((addr >= PPC44x_PCIMEM_LO) && (addr <= PPC44x_PCIMEM_HI))
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page_4gb = PPC44x_PCIMEM_PAGE;
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return (page_4gb | addr);
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};
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EXPORT_SYMBOL(fixup_bigphys_addr);
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void __init ibm44x_calibrate_decr(unsigned int freq)
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{
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tb_ticks_per_jiffy = freq / HZ;
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tb_to_us = mulhwu_scale_factor(freq, 1000000);
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/* Set the time base to zero */
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mtspr(SPRN_TBWL, 0);
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mtspr(SPRN_TBWU, 0);
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/* Clear any pending timer interrupts */
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mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
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/* Enable decrementer interrupt */
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mtspr(SPRN_TCR, TCR_DIE);
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}
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extern void abort(void);
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static void ibm44x_restart(char *cmd)
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{
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local_irq_disable();
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abort();
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}
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static void ibm44x_power_off(void)
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{
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local_irq_disable();
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for(;;);
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}
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static void ibm44x_halt(void)
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{
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local_irq_disable();
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for(;;);
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}
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/*
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* Read the 44x memory controller to get size of system memory.
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*/
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static unsigned long __init ibm44x_find_end_of_memory(void)
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{
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u32 i, bank_config;
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u32 mem_size = 0;
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for (i=0; i<4; i++)
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{
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switch (i)
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{
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case 0:
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mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B0CR);
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break;
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case 1:
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mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B1CR);
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break;
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case 2:
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mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B2CR);
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break;
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case 3:
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mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B3CR);
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break;
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}
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bank_config = mfdcr(DCRN_SDRAM0_CFGDATA);
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if (!(bank_config & SDRAM_CONFIG_BANK_ENABLE))
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continue;
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switch (SDRAM_CONFIG_BANK_SIZE(bank_config))
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{
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case SDRAM_CONFIG_SIZE_8M:
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mem_size += PPC44x_MEM_SIZE_8M;
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break;
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case SDRAM_CONFIG_SIZE_16M:
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mem_size += PPC44x_MEM_SIZE_16M;
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break;
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case SDRAM_CONFIG_SIZE_32M:
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mem_size += PPC44x_MEM_SIZE_32M;
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break;
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case SDRAM_CONFIG_SIZE_64M:
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mem_size += PPC44x_MEM_SIZE_64M;
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break;
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case SDRAM_CONFIG_SIZE_128M:
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mem_size += PPC44x_MEM_SIZE_128M;
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break;
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case SDRAM_CONFIG_SIZE_256M:
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mem_size += PPC44x_MEM_SIZE_256M;
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break;
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case SDRAM_CONFIG_SIZE_512M:
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mem_size += PPC44x_MEM_SIZE_512M;
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break;
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}
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}
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return mem_size;
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}
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void __init ibm44x_platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
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unsigned long r6, unsigned long r7)
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{
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parse_bootinfo(find_bootinfo());
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/*
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* If we were passed in a board information, copy it into the
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* residual data area.
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*/
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if (r3)
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__res = *(bd_t *)(r3 + KERNELBASE);
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#if defined(CONFIG_BLK_DEV_INITRD)
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/*
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* If the init RAM disk has been configured in, and there's a valid
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* starting address for it, set it up.
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*/
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if (r4) {
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initrd_start = r4 + KERNELBASE;
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initrd_end = r5 + KERNELBASE;
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}
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#endif /* CONFIG_BLK_DEV_INITRD */
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/* Copy the kernel command line arguments to a safe place. */
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if (r6) {
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*(char *) (r7 + KERNELBASE) = 0;
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strcpy(cmd_line, (char *) (r6 + KERNELBASE));
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}
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ppc_md.init_IRQ = ppc4xx_pic_init;
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ppc_md.find_end_of_memory = ibm44x_find_end_of_memory;
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ppc_md.restart = ibm44x_restart;
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ppc_md.power_off = ibm44x_power_off;
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ppc_md.halt = ibm44x_halt;
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#ifdef CONFIG_SERIAL_TEXT_DEBUG
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ppc_md.progress = gen550_progress;
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#endif /* CONFIG_SERIAL_TEXT_DEBUG */
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#ifdef CONFIG_KGDB
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ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
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#endif
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/*
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* The Abatron BDI JTAG debugger does not tolerate others
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* mucking with the debug registers.
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*/
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#if !defined(CONFIG_BDI_SWITCH)
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/* Enable internal debug mode */
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mtspr(SPRN_DBCR0, (DBCR0_IDM));
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/* Clear any residual debug events */
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mtspr(SPRN_DBSR, 0xffffffff);
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#endif
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}
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/* Called from machine_check_exception */
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void platform_machine_check(struct pt_regs *regs)
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{
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#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
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printk("PLB0: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x%08x\n",
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mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL),
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mfdcr(DCRN_PLB0_ACR), mfdcr(DCRN_PLB0_BESRH),
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mfdcr(DCRN_PLB0_BESRL));
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printk("PLB1: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x%08x\n",
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mfdcr(DCRN_PLB1_BEARH), mfdcr(DCRN_PLB1_BEARL),
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mfdcr(DCRN_PLB1_ACR), mfdcr(DCRN_PLB1_BESRH),
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mfdcr(DCRN_PLB1_BESRL));
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#else
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printk("PLB0: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x\n",
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mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL),
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mfdcr(DCRN_PLB0_ACR), mfdcr(DCRN_PLB0_BESR));
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#endif
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printk("POB0: BEAR=0x%08x%08x BESR0=0x%08x BESR1=0x%08x\n",
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mfdcr(DCRN_POB0_BEARH), mfdcr(DCRN_POB0_BEARL),
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mfdcr(DCRN_POB0_BESR0), mfdcr(DCRN_POB0_BESR1));
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printk("OPB0: BEAR=0x%08x%08x BSTAT=0x%08x\n",
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mfdcr(DCRN_OPB0_BEARH), mfdcr(DCRN_OPB0_BEARL),
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mfdcr(DCRN_OPB0_BSTAT));
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}
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