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Mark Salter 25b48ff852 C6X: fix timer64 initialization ... Some SoCs have a timer block enable controlled through the DSCR registers. There is a problem in the timer64 driver initialization where the code accesses a timer register to get the divisor used to calculate timer clock rate. If the timer block has not been enabled when this register read takes place, an exception is generated. This patch makes sure that the timer block is enabled before accessing the registers. Signed-off-by: Mark Salter <msalter@redhat.com>		13 years ago
..
Kconfig	…
Makefile	…
cache.c	C6X: cache control	14 years ago
dscr.c	C6X: DSCR - Device State Configuration Registers	14 years ago
emif.c	C6X: fix layout of EMIFA registers	13 years ago
megamod-pic.c	…
platform.c	…
pll.c	C6X: clocks	14 years ago
plldata.c	C6X: clocks	14 years ago
timer64.c	C6X: fix timer64 initialization	13 years ago