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473 lines
14 KiB
473 lines
14 KiB
/*
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* Author: Dale Farnsworth <dale.farnsworth@mvista.com>
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*
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* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/types.h>
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#include <linux/major.h>
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#include <linux/initrd.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/ide.h>
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#include <linux/root_dev.h>
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#include <linux/harrier_defs.h>
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#include <asm/byteorder.h>
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#include <asm/system.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/dma.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/machdep.h>
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#include <asm/time.h>
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#include <asm/pci-bridge.h>
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#include <asm/open_pic.h>
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#include <asm/bootinfo.h>
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#include <asm/harrier.h>
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#include "prpmc800.h"
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#define HARRIER_REVI_REG (PRPMC800_HARRIER_XCSR_BASE+HARRIER_REVI_OFF)
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#define HARRIER_UCTL_REG (PRPMC800_HARRIER_XCSR_BASE+HARRIER_UCTL_OFF)
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#define HARRIER_MISC_CSR_REG (PRPMC800_HARRIER_XCSR_BASE+HARRIER_MISC_CSR_OFF)
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#define HARRIER_IFEVP_REG (PRPMC800_HARRIER_MPIC_BASE+HARRIER_MPIC_IFEVP_OFF)
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#define HARRIER_IFEDE_REG (PRPMC800_HARRIER_MPIC_BASE+HARRIER_MPIC_IFEDE_OFF)
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#define HARRIER_FEEN_REG (PRPMC800_HARRIER_XCSR_BASE+HARRIER_FEEN_OFF)
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#define HARRIER_FEMA_REG (PRPMC800_HARRIER_XCSR_BASE+HARRIER_FEMA_OFF)
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#define HARRIER_VENI_REG (PRPMC800_HARRIER_XCSR_BASE + HARRIER_VENI_OFF)
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#define HARRIER_MISC_CSR (PRPMC800_HARRIER_XCSR_BASE + \
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HARRIER_MISC_CSR_OFF)
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#define MONARCH (monarch != 0)
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#define NON_MONARCH (monarch == 0)
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extern int mpic_init(void);
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extern unsigned long loops_per_jiffy;
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extern void gen550_progress(char *, unsigned short);
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static int monarch = 0;
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static int found_self = 0;
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static int self = 0;
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static u_char prpmc800_openpic_initsenses[] __initdata =
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{
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_HOSTINT0 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_UNUSED */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_DEBUGINT */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_HARRIER_WDT */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_UNUSED */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_UNUSED */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_HOSTINT1 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_HOSTINT2 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_HOSTINT3 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_PMC_INTA */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_PMC_INTB */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_PMC_INTC */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_PMC_INTD */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_UNUSED */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_UNUSED */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_UNUSED */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PRPMC800_INT_HARRIER_INT (UARTS, ABORT, DMA) */
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};
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/*
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* Motorola PrPMC750/PrPMC800 in PrPMCBASE or PrPMC-Carrier
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* Combined irq tables. Only Base has IDSEL 14, only Carrier has 21 and 22.
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*/
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static inline int
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prpmc_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
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{
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static char pci_irq_table[][4] =
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/*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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{
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{12, 0, 0, 0}, /* IDSEL 14 - Ethernet, base */
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{0, 0, 0, 0}, /* IDSEL 15 - unused */
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{10, 11, 12, 9}, /* IDSEL 16 - PMC A1, PMC1 */
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{10, 11, 12, 9}, /* IDSEL 17 - PrPMC-A-B, PMC2-B */
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{11, 12, 9, 10}, /* IDSEL 18 - PMC A1-B, PMC1-B */
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{0, 0, 0, 0}, /* IDSEL 19 - unused */
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{9, 10, 11, 12}, /* IDSEL 20 - P2P Bridge */
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{11, 12, 9, 10}, /* IDSEL 21 - PMC A2, carrier */
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{12, 9, 10, 11}, /* IDSEL 22 - PMC A2-B, carrier */
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};
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const long min_idsel = 14, max_idsel = 22, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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};
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static int
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prpmc_read_config_dword(struct pci_controller *hose, u8 bus, u8 devfn,
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int offset, u32 * val)
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{
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/* paranoia */
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if ((hose == NULL) ||
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(hose->cfg_addr == NULL) || (hose->cfg_data == NULL))
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return PCIBIOS_DEVICE_NOT_FOUND;
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out_be32(hose->cfg_addr, ((offset & 0xfc) << 24) | (devfn << 16)
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| ((bus - hose->bus_offset) << 8) | 0x80);
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*val = in_le32((u32 *) (hose->cfg_data + (offset & 3)));
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return PCIBIOS_SUCCESSFUL;
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}
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#define HARRIER_PCI_VEND_DEV_ID (PCI_VENDOR_ID_MOTOROLA | \
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(PCI_DEVICE_ID_MOTOROLA_HARRIER << 16))
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static int prpmc_self(u8 bus, u8 devfn)
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{
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/*
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* Harriers always view themselves as being on bus 0. If we're not
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* looking at bus 0, we're not going to find ourselves.
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*/
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if (bus != 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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else {
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int result;
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int val;
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struct pci_controller *hose;
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hose = pci_bus_to_hose(bus);
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/* See if target device is a Harrier */
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result = prpmc_read_config_dword(hose, bus, devfn,
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PCI_VENDOR_ID, &val);
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if ((result != PCIBIOS_SUCCESSFUL) ||
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(val != HARRIER_PCI_VEND_DEV_ID))
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* LBA bit is set if target Harrier == initiating Harrier
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* (i.e. if we are reading our own PCI header).
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*/
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result = prpmc_read_config_dword(hose, bus, devfn,
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HARRIER_LBA_OFF, &val);
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if ((result != PCIBIOS_SUCCESSFUL) ||
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((val & HARRIER_LBA_MSK) != HARRIER_LBA_MSK))
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return PCIBIOS_DEVICE_NOT_FOUND;
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/* It's us, save our location for later */
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self = devfn;
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found_self = 1;
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return PCIBIOS_SUCCESSFUL;
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}
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}
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static int prpmc_exclude_device(u8 bus, u8 devfn)
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{
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/*
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* Monarch is allowed to access all PCI devices. Non-monarch is
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* only allowed to access its own Harrier.
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*/
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if (MONARCH)
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return PCIBIOS_SUCCESSFUL;
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if (found_self)
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if ((bus == 0) && (devfn == self))
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return PCIBIOS_SUCCESSFUL;
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else
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return PCIBIOS_DEVICE_NOT_FOUND;
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else
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return prpmc_self(bus, devfn);
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}
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void __init prpmc800_find_bridges(void)
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{
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struct pci_controller *hose;
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int host_bridge;
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hose = pcibios_alloc_controller();
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if (!hose)
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return;
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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ppc_md.pci_exclude_device = prpmc_exclude_device;
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ppc_md.pcibios_fixup = NULL;
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ppc_md.pcibios_fixup_bus = NULL;
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ppc_md.pci_swizzle = common_swizzle;
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ppc_md.pci_map_irq = prpmc_map_irq;
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setup_indirect_pci(hose,
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PRPMC800_PCI_CONFIG_ADDR, PRPMC800_PCI_CONFIG_DATA);
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/* Get host bridge vendor/dev id */
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host_bridge = in_be32((uint *) (HARRIER_VENI_REG));
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if (host_bridge != HARRIER_VEND_DEV_ID) {
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printk(KERN_CRIT "Host bridge 0x%x not supported\n",
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host_bridge);
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return;
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}
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monarch = in_be32((uint *) HARRIER_MISC_CSR) & HARRIER_SYSCON;
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printk(KERN_INFO "Running as %s.\n",
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MONARCH ? "Monarch" : "Non-Monarch");
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hose->io_space.start = PRPMC800_PCI_IO_START;
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hose->io_space.end = PRPMC800_PCI_IO_END;
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hose->io_base_virt = (void *)PRPMC800_ISA_IO_BASE;
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hose->pci_mem_offset = PRPMC800_PCI_PHY_MEM_OFFSET;
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pci_init_resource(&hose->io_resource,
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PRPMC800_PCI_IO_START, PRPMC800_PCI_IO_END,
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IORESOURCE_IO, "PCI host bridge");
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if (MONARCH) {
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hose->mem_space.start = PRPMC800_PCI_MEM_START;
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hose->mem_space.end = PRPMC800_PCI_MEM_END;
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pci_init_resource(&hose->mem_resources[0],
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PRPMC800_PCI_MEM_START,
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PRPMC800_PCI_MEM_END,
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IORESOURCE_MEM, "PCI host bridge");
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if (harrier_init(hose,
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PRPMC800_HARRIER_XCSR_BASE,
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PRPMC800_PROC_PCI_MEM_START,
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PRPMC800_PROC_PCI_MEM_END,
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PRPMC800_PROC_PCI_IO_START,
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PRPMC800_PROC_PCI_IO_END,
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PRPMC800_HARRIER_MPIC_BASE) != 0)
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printk(KERN_CRIT "Could not initialize HARRIER "
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"bridge\n");
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harrier_release_eready(PRPMC800_HARRIER_XCSR_BASE);
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harrier_wait_eready(PRPMC800_HARRIER_XCSR_BASE);
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hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
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} else {
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pci_init_resource(&hose->mem_resources[0],
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PRPMC800_NM_PCI_MEM_START,
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PRPMC800_NM_PCI_MEM_END,
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IORESOURCE_MEM, "PCI host bridge");
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hose->mem_space.start = PRPMC800_NM_PCI_MEM_START;
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hose->mem_space.end = PRPMC800_NM_PCI_MEM_END;
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if (harrier_init(hose,
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PRPMC800_HARRIER_XCSR_BASE,
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PRPMC800_NM_PROC_PCI_MEM_START,
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PRPMC800_NM_PROC_PCI_MEM_END,
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PRPMC800_PROC_PCI_IO_START,
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PRPMC800_PROC_PCI_IO_END,
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PRPMC800_HARRIER_MPIC_BASE) != 0)
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printk(KERN_CRIT "Could not initialize HARRIER "
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"bridge\n");
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harrier_setup_nonmonarch(PRPMC800_HARRIER_XCSR_BASE,
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HARRIER_ITSZ_1MB);
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harrier_release_eready(PRPMC800_HARRIER_XCSR_BASE);
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}
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}
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static int prpmc800_show_cpuinfo(struct seq_file *m)
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{
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seq_printf(m, "machine\t\t: PrPMC800\n");
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return 0;
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}
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static void __init prpmc800_setup_arch(void)
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{
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/* init to some ~sane value until calibrate_delay() runs */
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loops_per_jiffy = 50000000 / HZ;
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/* Lookup PCI host bridges */
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prpmc800_find_bridges();
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#ifdef CONFIG_BLK_DEV_INITRD
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if (initrd_start)
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ROOT_DEV = Root_RAM0;
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else
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#endif
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#ifdef CONFIG_ROOT_NFS
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ROOT_DEV = Root_NFS;
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#else
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ROOT_DEV = Root_SDA2;
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#endif
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printk(KERN_INFO "Port by MontaVista Software, Inc. "
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"(source@mvista.com)\n");
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}
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/*
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* Compute the PrPMC800's tbl frequency using the baud clock as a reference.
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*/
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static void __init prpmc800_calibrate_decr(void)
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{
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unsigned long tbl_start, tbl_end;
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unsigned long current_state, old_state, tb_ticks_per_second;
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unsigned int count;
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unsigned int harrier_revision;
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harrier_revision = readb(HARRIER_REVI_REG);
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if (harrier_revision < 2) {
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/* XTAL64 was broken in harrier revision 1 */
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printk(KERN_INFO "time_init: Harrier revision %d, assuming "
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"100 Mhz bus\n", harrier_revision);
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tb_ticks_per_second = 100000000 / 4;
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tb_ticks_per_jiffy = tb_ticks_per_second / HZ;
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tb_to_us = mulhwu_scale_factor(tb_ticks_per_second, 1000000);
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return;
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}
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/*
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* The XTAL64 bit oscillates at the 1/64 the base baud clock
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* Set count to XTAL64 cycles per second. Since we'll count
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* half-cycles, we'll reach the count in half a second.
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*/
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count = PRPMC800_BASE_BAUD / 64;
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/* Find the first edge of the baud clock */
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old_state = readb(HARRIER_UCTL_REG) & HARRIER_XTAL64_MASK;
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do {
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current_state = readb(HARRIER_UCTL_REG) & HARRIER_XTAL64_MASK;
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} while (old_state == current_state);
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old_state = current_state;
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/* Get the starting time base value */
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tbl_start = get_tbl();
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/*
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* Loop until we have found a number of edges (half-cycles)
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* equal to the count (half a second)
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*/
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do {
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do {
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current_state = readb(HARRIER_UCTL_REG) &
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HARRIER_XTAL64_MASK;
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} while (old_state == current_state);
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old_state = current_state;
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} while (--count);
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/* Get the ending time base value */
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tbl_end = get_tbl();
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/* We only counted for half a second, so double to get ticks/second */
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tb_ticks_per_second = (tbl_end - tbl_start) * 2;
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tb_ticks_per_jiffy = tb_ticks_per_second / HZ;
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tb_to_us = mulhwu_scale_factor(tb_ticks_per_second, 1000000);
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}
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static void prpmc800_restart(char *cmd)
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{
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ulong temp;
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local_irq_disable();
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temp = in_be32((uint *) HARRIER_MISC_CSR_REG);
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temp |= HARRIER_RSTOUT;
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out_be32((uint *) HARRIER_MISC_CSR_REG, temp);
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while (1) ;
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}
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static void prpmc800_halt(void)
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{
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local_irq_disable();
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while (1) ;
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}
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static void prpmc800_power_off(void)
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{
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prpmc800_halt();
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}
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static void __init prpmc800_init_IRQ(void)
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{
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OpenPIC_InitSenses = prpmc800_openpic_initsenses;
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OpenPIC_NumInitSenses = sizeof(prpmc800_openpic_initsenses);
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/* Setup external interrupt sources. */
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openpic_set_sources(0, 16, OpenPIC_Addr + 0x10000);
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/* Setup internal UART interrupt source. */
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openpic_set_sources(16, 1, OpenPIC_Addr + 0x10200);
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/* Do the MPIC initialization based on the above settings. */
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openpic_init(0);
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/* enable functional exceptions for uarts and abort */
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out_8((u8 *) HARRIER_FEEN_REG, (HARRIER_FE_UA0 | HARRIER_FE_UA1));
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out_8((u8 *) HARRIER_FEMA_REG, ~(HARRIER_FE_UA0 | HARRIER_FE_UA1));
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}
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/*
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* Set BAT 3 to map 0xf0000000 to end of physical memory space.
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*/
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static __inline__ void prpmc800_set_bat(void)
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{
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mb();
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mtspr(SPRN_DBAT1U, 0xf0001ffe);
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mtspr(SPRN_DBAT1L, 0xf000002a);
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mb();
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}
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/*
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* We need to read the Harrier memory controller
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* to properly determine this value
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*/
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static unsigned long __init prpmc800_find_end_of_memory(void)
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{
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/* Read the memory size from the Harrier XCSR */
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return harrier_get_mem_size(PRPMC800_HARRIER_XCSR_BASE);
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}
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static void __init prpmc800_map_io(void)
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{
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io_block_mapping(0x80000000, 0x80000000, 0x10000000, _PAGE_IO);
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io_block_mapping(0xf0000000, 0xf0000000, 0x10000000, _PAGE_IO);
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}
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void __init
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platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
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unsigned long r6, unsigned long r7)
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{
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parse_bootinfo(find_bootinfo());
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prpmc800_set_bat();
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isa_io_base = PRPMC800_ISA_IO_BASE;
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isa_mem_base = PRPMC800_ISA_MEM_BASE;
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pci_dram_offset = PRPMC800_PCI_DRAM_OFFSET;
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ppc_md.setup_arch = prpmc800_setup_arch;
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ppc_md.show_cpuinfo = prpmc800_show_cpuinfo;
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ppc_md.init_IRQ = prpmc800_init_IRQ;
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ppc_md.get_irq = openpic_get_irq;
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|
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ppc_md.find_end_of_memory = prpmc800_find_end_of_memory;
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ppc_md.setup_io_mappings = prpmc800_map_io;
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ppc_md.restart = prpmc800_restart;
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ppc_md.power_off = prpmc800_power_off;
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ppc_md.halt = prpmc800_halt;
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|
|
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/* PrPMC800 has no timekeeper part */
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ppc_md.time_init = NULL;
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ppc_md.get_rtc_time = NULL;
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ppc_md.set_rtc_time = NULL;
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ppc_md.calibrate_decr = prpmc800_calibrate_decr;
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#ifdef CONFIG_SERIAL_TEXT_DEBUG
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ppc_md.progress = gen550_progress;
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#else /* !CONFIG_SERIAL_TEXT_DEBUG */
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ppc_md.progress = NULL;
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#endif /* CONFIG_SERIAL_TEXT_DEBUG */
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}
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