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358 lines
9.9 KiB
358 lines
9.9 KiB
/*
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* Copyright (C) 2005 - 2010 ServerEngines
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation. The full GNU General
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* Public License is included in this distribution in the file called COPYING.
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*
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* Contact Information:
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* linux-drivers@serverengines.com
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*
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* ServerEngines
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* 209 N. Fair Oaks Ave
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* Sunnyvale, CA 94085
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*/
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/********* Mailbox door bell *************/
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/* Used for driver communication with the FW.
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* The software must write this register twice to post any command. First,
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* it writes the register with hi=1 and the upper bits of the physical address
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* for the MAILBOX structure. Software must poll the ready bit until this
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* is acknowledged. Then, sotware writes the register with hi=0 with the lower
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* bits in the address. It must poll the ready bit until the command is
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* complete. Upon completion, the MAILBOX will contain a valid completion
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* queue entry.
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*/
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#define MPU_MAILBOX_DB_OFFSET 0x160
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#define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */
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#define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */
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#define MPU_EP_CONTROL 0
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/********** MPU semphore ******************/
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#define MPU_EP_SEMAPHORE_OFFSET 0xac
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#define EP_SEMAPHORE_POST_STAGE_MASK 0x0000FFFF
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#define EP_SEMAPHORE_POST_ERR_MASK 0x1
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#define EP_SEMAPHORE_POST_ERR_SHIFT 31
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/* MPU semphore POST stage values */
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#define POST_STAGE_AWAITING_HOST_RDY 0x1 /* FW awaiting goahead from host */
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#define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
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#define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */
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#define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
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/********* Memory BAR register ************/
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#define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
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/* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
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* Disable" may still globally block interrupts in addition to individual
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* interrupt masks; a mechanism for the device driver to block all interrupts
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* atomically without having to arbitrate for the PCI Interrupt Disable bit
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* with the OS.
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*/
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#define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
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/********* Power managment (WOL) **********/
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#define PCICFG_PM_CONTROL_OFFSET 0x44
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#define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */
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/********* ISR0 Register offset **********/
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#define CEV_ISR0_OFFSET 0xC18
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#define CEV_ISR_SIZE 4
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/********* Event Q door bell *************/
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#define DB_EQ_OFFSET DB_CQ_OFFSET
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#define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
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/* Clear the interrupt for this eq */
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#define DB_EQ_CLR_SHIFT (9) /* bit 9 */
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/* Must be 1 */
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#define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
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/* Number of event entries processed */
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#define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
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/* Rearm bit */
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#define DB_EQ_REARM_SHIFT (29) /* bit 29 */
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/********* Compl Q door bell *************/
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#define DB_CQ_OFFSET 0x120
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#define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
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/* Number of event entries processed */
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#define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
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/* Rearm bit */
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#define DB_CQ_REARM_SHIFT (29) /* bit 29 */
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/********** TX ULP door bell *************/
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#define DB_TXULP1_OFFSET 0x60
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#define DB_TXULP_RING_ID_MASK 0x7FF /* bits 0 - 10 */
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/* Number of tx entries posted */
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#define DB_TXULP_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
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#define DB_TXULP_NUM_POSTED_MASK 0x3FFF /* bits 16 - 29 */
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/********** RQ(erx) door bell ************/
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#define DB_RQ_OFFSET 0x100
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#define DB_RQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
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/* Number of rx frags posted */
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#define DB_RQ_NUM_POSTED_SHIFT (24) /* bits 24 - 31 */
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/********** MCC door bell ************/
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#define DB_MCCQ_OFFSET 0x140
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#define DB_MCCQ_RING_ID_MASK 0x7FF /* bits 0 - 10 */
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/* Number of entries posted */
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#define DB_MCCQ_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
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/* Flashrom related descriptors */
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#define IMAGE_TYPE_FIRMWARE 160
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#define IMAGE_TYPE_BOOTCODE 224
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#define IMAGE_TYPE_OPTIONROM 32
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#define NUM_FLASHDIR_ENTRIES 32
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#define IMG_TYPE_ISCSI_ACTIVE 0
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#define IMG_TYPE_REDBOOT 1
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#define IMG_TYPE_BIOS 2
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#define IMG_TYPE_PXE_BIOS 3
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#define IMG_TYPE_FCOE_BIOS 8
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#define IMG_TYPE_ISCSI_BACKUP 9
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#define IMG_TYPE_FCOE_FW_ACTIVE 10
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#define IMG_TYPE_FCOE_FW_BACKUP 11
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#define IMG_TYPE_NCSI_FW 13
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#define FLASHROM_OPER_FLASH 1
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#define FLASHROM_OPER_SAVE 2
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#define FLASHROM_OPER_REPORT 4
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#define FLASH_IMAGE_MAX_SIZE_g2 (1310720) /* Max firmware image sz */
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#define FLASH_BIOS_IMAGE_MAX_SIZE_g2 (262144) /* Max OPTION ROM img sz */
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#define FLASH_REDBOOT_IMAGE_MAX_SIZE_g2 (262144) /* Max Redboot image sz */
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#define FLASH_IMAGE_MAX_SIZE_g3 (2097152) /* Max fw image size */
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#define FLASH_BIOS_IMAGE_MAX_SIZE_g3 (524288) /* Max OPTION ROM img sz */
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#define FLASH_REDBOOT_IMAGE_MAX_SIZE_g3 (1048576) /* Max Redboot image sz */
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#define FLASH_NCSI_IMAGE_MAX_SIZE_g3 (262144) /* Max NSCI image sz */
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#define FLASH_NCSI_MAGIC (0x16032009)
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#define FLASH_NCSI_DISABLED (0)
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#define FLASH_NCSI_ENABLED (1)
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#define FLASH_NCSI_BITFILE_HDR_OFFSET (0x600000)
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/* Offsets for components on Flash. */
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#define FLASH_iSCSI_PRIMARY_IMAGE_START_g2 (1048576)
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#define FLASH_iSCSI_BACKUP_IMAGE_START_g2 (2359296)
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#define FLASH_FCoE_PRIMARY_IMAGE_START_g2 (3670016)
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#define FLASH_FCoE_BACKUP_IMAGE_START_g2 (4980736)
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#define FLASH_iSCSI_BIOS_START_g2 (7340032)
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#define FLASH_PXE_BIOS_START_g2 (7864320)
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#define FLASH_FCoE_BIOS_START_g2 (524288)
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#define FLASH_REDBOOT_START_g2 (0)
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#define FLASH_NCSI_START_g3 (15990784)
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#define FLASH_iSCSI_PRIMARY_IMAGE_START_g3 (2097152)
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#define FLASH_iSCSI_BACKUP_IMAGE_START_g3 (4194304)
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#define FLASH_FCoE_PRIMARY_IMAGE_START_g3 (6291456)
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#define FLASH_FCoE_BACKUP_IMAGE_START_g3 (8388608)
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#define FLASH_iSCSI_BIOS_START_g3 (12582912)
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#define FLASH_PXE_BIOS_START_g3 (13107200)
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#define FLASH_FCoE_BIOS_START_g3 (13631488)
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#define FLASH_REDBOOT_START_g3 (262144)
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/*
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* BE descriptors: host memory data structures whose formats
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* are hardwired in BE silicon.
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*/
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/* Event Queue Descriptor */
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#define EQ_ENTRY_VALID_MASK 0x1 /* bit 0 */
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#define EQ_ENTRY_RES_ID_MASK 0xFFFF /* bits 16 - 31 */
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#define EQ_ENTRY_RES_ID_SHIFT 16
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struct be_eq_entry {
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u32 evt;
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};
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/* TX Queue Descriptor */
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#define ETH_WRB_FRAG_LEN_MASK 0xFFFF
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struct be_eth_wrb {
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u32 frag_pa_hi; /* dword 0 */
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u32 frag_pa_lo; /* dword 1 */
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u32 rsvd0; /* dword 2 */
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u32 frag_len; /* dword 3: bits 0 - 15 */
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} __packed;
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/* Pseudo amap definition for eth_hdr_wrb in which each bit of the
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* actual structure is defined as a byte : used to calculate
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* offset/shift/mask of each field */
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struct amap_eth_hdr_wrb {
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u8 rsvd0[32]; /* dword 0 */
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u8 rsvd1[32]; /* dword 1 */
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u8 complete; /* dword 2 */
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u8 event;
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u8 crc;
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u8 forward;
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u8 ipsec;
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u8 mgmt;
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u8 ipcs;
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u8 udpcs;
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u8 tcpcs;
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u8 lso;
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u8 vlan;
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u8 gso[2];
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u8 num_wrb[5];
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u8 lso_mss[14];
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u8 len[16]; /* dword 3 */
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u8 vlan_tag[16];
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} __packed;
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struct be_eth_hdr_wrb {
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u32 dw[4];
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};
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/* TX Compl Queue Descriptor */
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/* Pseudo amap definition for eth_tx_compl in which each bit of the
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* actual structure is defined as a byte: used to calculate
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* offset/shift/mask of each field */
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struct amap_eth_tx_compl {
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u8 wrb_index[16]; /* dword 0 */
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u8 ct[2]; /* dword 0 */
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u8 port[2]; /* dword 0 */
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u8 rsvd0[8]; /* dword 0 */
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u8 status[4]; /* dword 0 */
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u8 user_bytes[16]; /* dword 1 */
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u8 nwh_bytes[8]; /* dword 1 */
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u8 lso; /* dword 1 */
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u8 cast_enc[2]; /* dword 1 */
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u8 rsvd1[5]; /* dword 1 */
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u8 rsvd2[32]; /* dword 2 */
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u8 pkts[16]; /* dword 3 */
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u8 ringid[11]; /* dword 3 */
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u8 hash_val[4]; /* dword 3 */
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u8 valid; /* dword 3 */
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} __packed;
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struct be_eth_tx_compl {
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u32 dw[4];
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};
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/* RX Queue Descriptor */
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struct be_eth_rx_d {
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u32 fragpa_hi;
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u32 fragpa_lo;
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};
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/* RX Compl Queue Descriptor */
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/* Pseudo amap definition for eth_rx_compl in which each bit of the
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* actual structure is defined as a byte: used to calculate
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* offset/shift/mask of each field */
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struct amap_eth_rx_compl {
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u8 vlan_tag[16]; /* dword 0 */
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u8 pktsize[14]; /* dword 0 */
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u8 port; /* dword 0 */
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u8 ip_opt; /* dword 0 */
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u8 err; /* dword 1 */
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u8 rsshp; /* dword 1 */
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u8 ipf; /* dword 1 */
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u8 tcpf; /* dword 1 */
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u8 udpf; /* dword 1 */
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u8 ipcksm; /* dword 1 */
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u8 l4_cksm; /* dword 1 */
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u8 ip_version; /* dword 1 */
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u8 macdst[6]; /* dword 1 */
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u8 vtp; /* dword 1 */
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u8 rsvd0; /* dword 1 */
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u8 fragndx[10]; /* dword 1 */
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u8 ct[2]; /* dword 1 */
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u8 sw; /* dword 1 */
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u8 numfrags[3]; /* dword 1 */
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u8 rss_flush; /* dword 2 */
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u8 cast_enc[2]; /* dword 2 */
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u8 vtm; /* dword 2 */
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u8 rss_bank; /* dword 2 */
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u8 rsvd1[23]; /* dword 2 */
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u8 lro_pkt; /* dword 2 */
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u8 rsvd2[2]; /* dword 2 */
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u8 valid; /* dword 2 */
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u8 rsshash[32]; /* dword 3 */
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} __packed;
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struct be_eth_rx_compl {
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u32 dw[4];
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};
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struct controller_id {
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u32 vendor;
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u32 device;
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u32 subvendor;
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u32 subdevice;
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};
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struct flash_comp {
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unsigned long offset;
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int optype;
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int size;
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};
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struct image_hdr {
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u32 imageid;
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u32 imageoffset;
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u32 imagelength;
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u32 image_checksum;
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u8 image_version[32];
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};
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struct flash_file_hdr_g2 {
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u8 sign[32];
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u32 cksum;
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u32 antidote;
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struct controller_id cont_id;
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u32 file_len;
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u32 chunk_num;
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u32 total_chunks;
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u32 num_imgs;
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u8 build[24];
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};
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struct flash_file_hdr_g3 {
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u8 sign[52];
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u8 ufi_version[4];
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u32 file_len;
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u32 cksum;
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u32 antidote;
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u32 num_imgs;
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u8 build[24];
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u8 rsvd[32];
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};
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struct flash_section_hdr {
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u32 format_rev;
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u32 cksum;
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u32 antidote;
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u32 build_no;
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u8 id_string[64];
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u32 active_entry_mask;
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u32 valid_entry_mask;
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u32 org_content_mask;
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u32 rsvd0;
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u32 rsvd1;
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u32 rsvd2;
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u32 rsvd3;
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u32 rsvd4;
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};
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struct flash_section_entry {
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u32 type;
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u32 offset;
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u32 pad_size;
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u32 image_size;
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u32 cksum;
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u32 entry_point;
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u32 rsvd0;
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u32 rsvd1;
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u8 ver_data[32];
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};
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struct flash_section_info {
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u8 cookie[32];
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struct flash_section_hdr fsec_hdr;
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struct flash_section_entry fsec_entry[32];
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};
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