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55 lines
1.5 KiB
55 lines
1.5 KiB
/*
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* Bubinga board definitions
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*
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* Copyright (c) 2005 DENX Software Engineering
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* Stefan Roese <sr@denx.de>
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*
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* Based on original work by
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* SAW (IBM)
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* 2003 (c) MontaVista Softare Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifdef __KERNEL__
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#ifndef __BUBINGA_H__
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#define __BUBINGA_H__
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#include <linux/config.h>
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#include <platforms/4xx/ibm405ep.h>
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#include <asm/ppcboot.h>
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/* Memory map for the Bubinga board.
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* Generic 4xx plus RTC.
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*/
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#define BUBINGA_RTC_PADDR ((uint)0xf0000000)
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#define BUBINGA_RTC_VADDR BUBINGA_RTC_PADDR
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#define BUBINGA_RTC_SIZE ((uint)8*1024)
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/* The UART clock is based off an internal clock -
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* define BASE_BAUD based on the internal clock and divider(s).
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* Since BASE_BAUD must be a constant, we will initialize it
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* using clock/divider values which OpenBIOS initializes
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* for typical configurations at various CPU speeds.
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* The base baud is calculated as (FWDA / EXT UART DIV / 16)
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*/
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#define BASE_BAUD 0
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/* Flash */
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#define PPC40x_FPGA_BASE 0xF0300000
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#define PPC40x_FPGA_REG_OFFS 1 /* offset to flash map reg */
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#define PPC40x_FLASH_ONBD_N(x) (x & 0x02)
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#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01)
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#define PPC40x_FLASH_LOW 0xFFF00000
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#define PPC40x_FLASH_HIGH 0xFFF80000
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#define PPC40x_FLASH_SIZE 0x80000
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#define PPC4xx_MACHINE_NAME "IBM Bubinga"
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#endif /* __BUBINGA_H__ */
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#endif /* __KERNEL__ */
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